Semiconductor device

• US 8,804,396 B2
• Filed: 10/22/2013
• Issued: 08/12/2014
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US14/059,475
• Publication Number:
  US 20140042511A1
• Time in Patent Office: 294 Days
• Field of Search: 365/63, 365/72, 365/145, 365/189.09, 365/189.11, 365/230.06, 365/227, 365/149
• US Class Current: 365/72
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 : including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Claims

1. A semiconductor device comprising:

a substrate containing a semiconductor material;

a semiconductor layer over the substrate;

a first transistor comprising a first source electrode, a first drain electrode, and a first gate electrode, the first transistor being a p-type transistor;

a second transistor comprising a second source electrode, a second drain electrode and a second gate electrode, one of the second source electrode and the second drain electrode being electrically connected to the first gate electrode;

a third transistor comprising a third source electrode, a third drain electrode and a third gate electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode; and

a capacitor electrically connected to the first gate electrode,

wherein a channel formation region of the first transistor is provided in the substrate, and

wherein a channel formation region of the second transistor is provided in the semiconductor layer formed over the substrate.

6. The semiconductor device according to claim 1,

wherein the second gate electrode is over the semiconductor layer, and

wherein the second source electrode and the second drain electrode are in direct contact with a top surface of the semiconductor layer.

7. The semiconductor device according to claim 1,

wherein the second gate electrode is over the oxide semiconductor layer, and

wherein the second source electrode and the second drain electrode are in direct contact with a top surface of the oxide semiconductor layer.

9. The semiconductor device according to claim 1, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

12. The semiconductor device according to claim 1, wherein the semiconductor layer is formed from an In—

Ga—

Zn—

O-based oxide semiconductor material.

15. A memory element comprising the semiconductor device according to claim 1.

18. An electronic appliance comprising the semiconductor device according to claim 1.

2. A semiconductor device comprising:

a substrate containing a semiconductor material;

an oxide semiconductor layer over the substrate;

a first transistor comprising a first source electrode, a first drain electrode, a first impurity region, a second impurity region, and a first gate electrode, the first impurity region and the second impurity region being formed in the substrate, and the first transistor being a p-type transistor;

a second transistor comprising a second source electrode, a second drain electrode and a second gate electrode, one of the second source electrode and the second drain electrode being electrically connected to the first gate electrode;

an oxide layer over the first transistor and below the second transistor, interposed between the first transistor and the second transistor;

a third transistor comprising a third source electrode, a third drain electrode and a third gate electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode; and

a capacitor electrically connected to the first gate electrode,

wherein a channel formation region of the first transistor is provided in the substrate, and

wherein a channel formation region of the second transistor is provided in the oxide semiconductor layer formed over the substrate.

3. The semiconductor device according to claim 2,

wherein the oxide layer is a aluminum oxide layer.

10. The semiconductor device according to claim 2, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

13. The semiconductor device according to claim 2, wherein the oxide semiconductor layer is formed from an In—

Ga—

Zn—

O-based oxide semiconductor material.

16. A memory element comprising the semiconductor device according to claim 2.

19. An electronic appliance comprising the semiconductor device according to claim 2.

4. A semiconductor device comprising:

a substrate containing a semiconductor material;

a row of memory cells and a column of memory cells, each memory cell comprising;

a semiconductor layer over the substrate;

a first transistor comprising a first source electrode, a first drain electrode, and a first gate electrode, the first transistor being a p-type transistor;

a second transistor comprising a second source electrode, a second drain electrode and a second gate electrode, one of the second source electrode and the second drain electrode being electrically connected to the first gate electrode;

a third transistor comprising a third source electrode, a third drain electrode and a third gate electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode; and

a capacitor electrically connected to the first gate electrode;

a first line electrically connected to the other ones of the first source electrodes and the first drain electrodes of the column of memory cells;

a second line electrically connected to the other ones of the second source electrodes and the second drain electrodes of the column of memory cells;

a third line electrically connected to the second gate electrodes of the row of memory cells; and

a fourth line electrically connected to the third gate electrodes of the row of memory cells,

wherein a channel formation region of the first transistor is provided in the substrate, and

wherein a channel formation region of the second transistor is provided in the semiconductor layer formed over the substrate.

5. The semiconductor device according to claim 4,

wherein the first line is a source line,

wherein the second line is a first signal line;

wherein the third line is a second signal line;

wherein the fourth line is a word line.

8. The semiconductor device according to claim 4,

wherein the second gate electrode is over the semiconductor layer, and

wherein the second source electrode and the second drain electrode are in direct contact with a top surface of the semiconductor layer.

11. The semiconductor device according to claim 4, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

14. The semiconductor device according to claim 4, wherein the semiconductor layer is formed from an In—

Ga—

Zn—

O-based oxide semiconductor material.

17. A memory cell array comprising the semiconductor device according to claim 4.

20. An electronic appliance comprising the semiconductor device according to claim 4.