Semiconductor memory device

• US 8,804,403 B2
• Filed: 08/16/2013
• Issued: 08/12/2014
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kushida, Keiichi
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US13/969,221
• Publication Number:
  US 20130336044A1
• Time in Patent Office: 361 Days
• Field of Search: 365/148, 365/154
• US Class Current: 365/148
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0072 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

Claims

1. A semiconductor memory device comprising a memory cell including:

a first driving transistor connected to a first storage node;

a first load transistor connected to the first storage node;

a first read transfer transistor connected between the first storage node and a first read bit line;

a first variable resistance element which has one terminal connected to the first storage node and has another terminal, a resistance of which changes depending on a voltage applied to both terminals;

a first write transfer transistor arranged between a first write bit line and the first variable resistance element;

a second driving transistor connected to a second storage node;

a second load transistor connected to the second storage node;

a second read transfer transistor arranged between the second storage node and a second read bit line;

a second write transfer transistor arranged between the second storage node and a second write bit line, wherein a source of the first driving transistor and a source of the second driving transistor are connected to a first supply voltage and data written to the first storage node is saved to the first variable resistance element in response to the first supply voltage changing between a plurality of different voltage levels.

2. The semiconductor memory device according to claim 1,

wherein the memory cell further includes a second variable resistance element arranged between the second storage node and the second write transfer transistor.

3. The semiconductor memory device according to claim 1, further comprising:

a plurality of the memory cells, each connected to the first read bit line and the first write bit line.

4. The semiconductor memory device according to claim 1,

wherein the memory cell further includes an equalizing transistor in which one of a source and a drain is connected to a gate of the first load transistor, and the other is connected to a gate of the second load transistor.

5. The semiconductor memory device according to claim 1,

wherein the first variable resistance element is a ReRAM memory device.

6. The semiconductor memory device according to claim 1,

wherein the first variable resistance element is an MRAM memory device.

7. The semiconductor memory device according to claim 1,

wherein the first variable resistance element is a FeRAM memory device.

8. The semiconductor memory device according to claim 1,

wherein the first variable resistance element includes one terminal electrically connected to the first storage node and the other terminal electrically connected to the first write transfer transistor, and

the first variable resistance element becomes a low resistance state when a low level is applied to the one terminal and a high level is applied to the other terminal and becomes a high resistance state when a high level is applied to the one terminal and a low level is applied to the other terminal.

9. The semiconductor memory device according to claim 8,

wherein the first write transfer transistor has both a function as a transfer gate in an operation of writing in the first storage node and a function as a control gate in a storing operation and a restoring operation between the first storage node and the first variable resistance element.

10. The semiconductor memory device according to claim 2,

wherein the second variable resistance element includes one terminal electrically connected to the second storage node and the other terminal electrically connected to the second write transfer transistor, and

the second variable resistance element becomes a low resistance state when a low level is applied to the one terminal and a high level is applied to the other terminal and becomes a high resistance state when a high level is applied to the one terminal and a low level is applied to the other terminal.

11. The semiconductor memory device according to claim 10,

wherein the second write transfer transistor has both a function as a transfer gate in an operation of writing in the second storage node and a function as a control gate in a storing operation and a restoring operation between the second storage node and the second variable resistance element.

12. The semiconductor memory device according to claim 1, wherein the plurality of different voltage levels includes:

a first potential that is substantially equal to VDD and that is H level potential at least for read operations of the memory cell;

a second potential that is different from the first potential and that is H level potential for set operation of the first variable resistance element; and

a third potential that is different from the first potential and the second potential and that is H level potential for reset operation of the first variable resistance element.

13. The semiconductor memory device according to claim 12,

wherein the first potential is H level potential for write operation and read operation of the memory cell.

14. The semiconductor memory device according to claim 1, wherein the plurality of different voltage levels includes:

a first potential that is substantially equal to VDD and that is H level potential for read and write operations of the memory cell;

or

a fourth potential that is lower than the first potential and that is L level potential for write operation of the memory cell.

15. The semiconductor memory device according to claim 4,

wherein a gate of the equalizing transistor is connected to a second power, and

the first power and the second power are changeable respectively.

16. The semiconductor memory device according to claim 15, wherein the second power becomes to be at H level during a partial time period in a time period when the first power becomes to be at L level.

17. The semiconductor memory device according to claim 16, wherein the partial time period corresponds to a first half of the time period.