Memory device and semiconductor device

• US 8,804,405 B2
• Filed: 06/11/2012
• Issued: 08/12/2014
• Est. Priority Date: 06/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime, Yamazaki, Shunpei
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US13/492,961
• Publication Number:
  US 20120320663A1
• Time in Patent Office: 792 Days
• Field of Search: 365/149, 365/233.1, 365/185.05
• US Class Current: 365/149
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A memory device with low power consumption is provided. A memory device includes a first logic element generating an output potential by inverting a polarity of a potential of a signal including data in accordance with a first clock signal; second and third logic elements holding the output potential generated by the first logic element; a switching element including a transistor; and a capacitor storing the data by being supplied with the output potential of the first logic element which is held by the second and third logic elements via the switching element. The second logic element generates an output potential by inverting a polarity of an output potential of the third logic element in accordance with a second clock signal different from the first clock signal, and the third logic element generates an output potential by inverting a polarity of the output potential of the second logic element.

Claims

1. A memory device comprising:

a first clocked inverter configured to be controlled by a first clock signal;

a first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first clocked inverter;

a second clocked inverter configured to be controlled by a second clock signal, wherein an input terminal of the second clocked inverter is electrically connected to an output terminal of the first inverter, and an output terminal of the second clocked inverter is electrically connected to the output terminal of the first clocked inverter and the input terminal of the first inverter;

a transistor, wherein one of a source and a drain of the transistor is electrically connected to the output terminal of the first clocked inverter, the input terminal of the first inverter, and the output terminal of the second clocked inverter; and

a capacitor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor,

wherein the first clocked inverter is configured to be controlled independently of the second clocked inverter, and

wherein the transistor comprises an oxide semiconductor in a channel formation region.

2. The memory device according to claim 1, wherein the oxide semiconductor comprises indium, gallium, and zinc.

3. The memory device according to claim 1, wherein the oxide semiconductor is a crystalline oxide semiconductor.

4. The memory device according to claim 1,

wherein each of the first clocked inverter, the second clocked inverter, and the first inverter comprises an n-channel type transistor and a p-channel type transistor, and

wherein each of the n-channel type transistor and the p-channel type transistor comprises silicon in a channel formation region.

5. The memory device according to claim 4,

wherein the n-channel type transistor and the p-channel type transistor are provided over a substrate, and

wherein the transistor is provided over the n-channel type transistor and the p-channel type transistor.

6. The memory device according to claim 4, wherein the channel formation region of the n-channel type transistor and the channel formation region of the p-channel type transistor are provided in a semiconductor substrate.

7. A semiconductor device comprising:

the memory device according to claim 1; and

an arithmetic logic unit operationally connected to the memory device.

8. A memory device comprising:

a first clocked inverter electrically connected to a first line configured to be supplied with a first clock signal and a second line configured to be supplied with an inverted signal of the first clock signal;

a first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first clocked inverter;

a second clocked inverter electrically connected to a third line configured to be supplied with a second clock signal and a fourth line configured to be supplied with an inverted signal of the second clock signal, wherein an input terminal of the second clocked inverter is electrically connected to an output terminal of the first inverter, and an output terminal of the second clocked inverter is electrically connected to the output terminal of the first clocked inverter and the input terminal of the first inverter;

a transistor, wherein one of a source and a drain of the transistor is electrically connected to the output terminal of the first clocked inverter, the input terminal of the first inverter, and the output terminal of the second clocked inverter; and

a capacitor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor,

wherein the transistor comprises an oxide semiconductor in a channel formation region.

9. The memory device according to claim 8, wherein the oxide semiconductor comprises indium, gallium, and zinc.

10. The memory device according to claim 8, wherein the oxide semiconductor is a crystalline oxide semiconductor.

11. The memory device according to claim 8,

wherein each of the first clocked inverter, the second clocked inverter, and the first inverter comprises an n-channel type transistor and a p-channel type transistor, and

wherein each of the n-channel type transistor and the p-channel type transistor comprises silicon in a channel formation region.

12. The memory device according to claim 11,

wherein the n-channel type transistor and the p-channel type transistor are provided over a substrate, and

wherein the transistor is provided over the n-channel type transistor and the p-channel type transistor.

13. The memory device according to claim 11, wherein the channel formation region of the n-channel type transistor and the channel formation region of the p-channel type transistor are provided in a semiconductor substrate.

14. A semiconductor device comprising:

the memory device according to claim 8; and

an arithmetic logic unit operationally connected to the memory device.

15. A memory device comprising:

a memory element comprising a plurality of inverters configured to hold one-bit data;

a transistor, wherein one of a source and a drain of the transistor is electrically connected to the memory element; and

a capacitor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor,

wherein the plurality of inverters comprises a first clocked inverter and a second clocked inverter,

wherein the first clocked inverter is configured to be controlled by a first clock signal,

wherein the second clocked inverter is configured to be controlled by a second clock signal,

wherein the first clocked inverter is configured to be controlled independently of the second clocked inverted, and

wherein the transistor comprises an oxide semiconductor in a channel formation region.

16. The memory device according to claim 15, wherein the oxide semiconductor comprises indium, gallium, and zinc.

17. The memory device according to claim 15, wherein the oxide semiconductor is a crystalline oxide semiconductor.

18. The memory device according to claim 15,

wherein each of the first clocked inverter and the second clocked inverter comprises an n-channel type transistor and a p-channel type transistor, and

wherein each of the n-channel type transistor and the p-channel type transistor comprises silicon in a channel formation region.

19. The memory device according to claim 18

wherein the n-channel type transistor and the p-channel type transistor are provided over a substrate, and

wherein the transistor is provided over the n-channel type transistor and the p-channel type transistor.

20. The memory device according to claim 18, wherein the channel formation region of the n-channel type transistor and the channel formation region of the p-channel type transistor are provided in a semiconductor substrate.

21. A semiconductor device comprising:

the memory device according to claim 15; and

an arithmetic logic unit operationally connected to the memory device.