PMOS pass gate

• US 8,804,407 B1
• Filed: 07/12/2011
• Issued: 08/12/2014
• Est. Priority Date: 07/12/2011
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Liu, Jun, Ratnakumar, Albert, Rahim, Irfan, Xiang, Qi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US13/181,219
• Time in Patent Office: 1,127 Days
• Field of Search: 365/156, 365/63
• US Class Current: 365/156
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

Claims

1. An integrated circuit (IC) comprising:

a memory cell; and

a pass gate coupled to the memory cell, wherein the pass gate comprises a p-channel metal oxide semiconductor (PMOS) transistor.

2. The IC of claim 1, wherein the PMOS transistor has a negative threshold voltage.

3. The IC of claim 1, wherein the PMOS transistor has a non-negative threshold voltage, a negative bias voltage is applied to the memory cell, and a negative gate voltage causes the pass gate to be in an ON state.

4. The IC of claim 1, wherein the memory cell is coupled to a gate of the pass gate and data stored in the memory cell controls a state of the pass gate.

5. The IC of claim 1, wherein the pass gate is a routing pass gate.

6. The IC of claim 1, wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a PMOS transistor, and wherein the NMOS transistor and the PMOS transistor of the CMOS inverter are thick oxide transistors.

7. The IC of claim 1 further comprising:

a configuration random access memory (RAM), wherein the configuration RAM includes the memory cell.

8. The IC of claim 1, wherein there is no well separation between transistors in the memory cell and the PMOS transistor of the pass gate.

9. The IC of claim 1, wherein the pass gate is coupled between a first line and a second line of a look up table (LUT).

10. The IC of claim 1, wherein the pass gate is coupled between a first interconnect line and a second interconnect line of the IC.

11. The IC of claim 1, wherein the IC is a programmable logic device.

12. A digital system comprising the IC of claim 1.

13. An integrated circuit (IC) comprising:

a configuration random access memory (RAM), wherein the configuration RAM includes a memory cell; and

a pass gate coupled to the memory cell, wherein the pass gate is a routing pass gate and comprises a p-channel metal oxide semiconductor (PMOS) transistor, further wherein the memory cell is coupled to a gate of the pass gate and data stored in the memory cell determines a state of the pass gate.

14. The IC of claim 13, wherein the PMOS transistor has a negative threshold voltage.

15. The IC of claim 13, wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a PMOS transistor, and wherein the NMOS transistor and the PMOS transistor of the CMOS inverter are thicker oxide transistors.

16. The IC of claim 13, wherein the pass gate is coupled between a first interconnect line and a second interconnect line of the IC.

17. An integrated circuit (IC) comprising:

a configuration random access memory (RAM), wherein the configuration RAM includes a memory cell, wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a p-channel metal oxide semiconductor (PMOS) transistor; and

a pass gate coupled to the memory cell, wherein the pass gate is a routing pass gate and comprises a PMOS transistor, further wherein the memory cell is coupled to a gate of the pass gate and data stored in the memory cell determines a state of the pass gate, further wherein the PMOS transistor of the pass gate has a negative threshold voltage.

18. The IC of claim 17, wherein the pass gate is coupled between a first interconnect line and a second interconnect line of the IC.

19. The IC of claim 17, wherein the pass gate is coupled between a first line and a second line of a look up table (LUT).

20. The IC of claim 17, wherein the IC is a programmable logic device.