Memory for a voltage regulator circuit

• US 8,804,440 B1
• Filed: 03/26/2014
• Issued: 08/12/2014
• Est. Priority Date: 10/15/2012
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Shi-Wen, Lu, Hsin-Pang, Tsai, Chung-Cheng, Mou, Ya-Nan
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/225,435
• Publication Number:
  US 20140211573A1
• Time in Patent Office: 139 Days
• Field of Search: 365/189.07, 365/189.09, 365/189.11, 365/230.06
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Claims

1. A memory, comprising:

a memory array comprising a plurality of source lines and a plurality of memory units, wherein each one of the source lines is electrically coupled to a respective group of memory units;

a decoder comprising an input terminal and a plurality of output terminals, the decoder being configured to have the output terminals thereof electrically coupled to the source lines, respectively; and

a voltage regulator circuit configured to provide a supply voltage to the input terminal of the decoder and electrically coupled to the output terminals of the decoder, the voltage regulator circuit being configured to generate a feedback signal according to a signal outputted from one output terminal of the decoder and a control signal, and consequently adjust the value of the supply voltage according to the feedback signal.

2. The memory according to claim 1, further comprising:

a supply voltage switch electrically coupled between an output terminal of the voltage regulator circuit and the input terminal of the decoder and configured to receive the supply voltage and a predetermined voltage and consequently selectively output, according to a control command, either the supply voltage or the predetermined voltage to the input terminal of the decoder.

3. The memory according to claim 1, wherein the control signal is generated according to a comparison result, the comparison result indicates the number of different bits existing between output data and input data of the memory array, and the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data.