Data interleaving module

• US 8,804,452 B2
• Filed: 07/31/2012
• Issued: 08/12/2014
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pilolli, Luigi, Gallese, Maria-Luisa, Castelli, Mauro
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/562,536
• Publication Number:
  US 20140040571A1
• Time in Patent Office: 742 Days
• Field of Search: 365/230.02, 365/185.03, 365/185.11, 365/189.02, 365/189.17
• US Class Current: 365/230.02
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 2212/254 Distributed memory
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Claims

1. A method, comprising:

interleaving data among a plurality of modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus, wherein interleaving the data comprises transferring amounts of the data corresponding to the selected data density from a bus to respective modules; and

transferring the interleaved data from the plurality of modules to a register.

2. The method of claim 1, wherein interleaving the data includes:

transferring a first amount of the data from the bus to a first module during a first clock cycle; and

transferring a second amount of the data from the bus to the first module during a second clock cycle, wherein the first amount and the second amount collectively correspond to the selected data density.

3. The method of claim 2, wherein interleaving the data includes:

transferring a third amount of the data from the bus to a second module during the first clock cycle, wherein the third amount corresponds to the selected data density.

4. The method of claim 1, wherein an amount of data corresponding to the selected data density comprises an amount equal to the data density.

5. The method of claim 1, wherein an amount of data corresponding to the selected data density comprises an amount proportional to the data density.

6. The method of claim 5, wherein B number of bytes are proportional to b number of bits, wherein the number B is equal to the number b.

7. A method, comprising:

receiving data from a plurality of portions of a register with a corresponding plurality of modules; and

deinterleaving the data with the plurality of modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus;

wherein deinterleaving the data comprises transferring the data from each of the plurality of modules to a bus shared by the plurality of modules such that an amount of data corresponding to the selected data density is output from each of the plurality of modules.

8. The method of claim 7, wherein deinterleaving the data comprises timing an output of the data from each of the plurality of modules to a bus shared by the plurality of modules such that an amount of data corresponding to the selected data density is output from each of the plurality of modules in turn.

9. The method of claim 7, wherein deinterleaving the data comprises:

transferring data from a first one of the plurality of modules to the bus during a particular clock cycle; and

transferring data from a second one of the plurality of modules to the bus during the particular clock cycle.

10. The method of claim 9, wherein deinterleaving the data comprises:

transferring an amount of data corresponding to the selected data density from the first one of the plurality of modules to the bus during the particular clock cycle; and

transferring an amount of data not corresponding to the selected data density from the second one of the plurality of modules to the bus during the particular clock cycle.

11. The method of claim 7, wherein deinterleaving the data comprises:

transferring an amount of data corresponding to the selected data density from the first one of the plurality of modules to the bus during a plurality of clock cycles; and

transferring an amount of data corresponding to the selected data density from the second one of the plurality of modules to the bus during the plurality of clock cycles.

12. An apparatus, comprising:

a plane of memory cells;

a register coupled to the plane of memory cells;

a plurality of modules coupled to the register; and

a bus coupled to the plurality of modules;

wherein the apparatus is configured to;

interleave data from the bus among the plurality of modules according to a selected one of a plurality of data densities per memory cell, wherein interleaving the data comprises transferring amounts of the data corresponding to the selected one of the plurality of data densities to respective modules; and

transfer the interleaved data to the register for programming to the plane of memory cells.

13. The apparatus of claim 12, wherein the apparatus is configured to interleave the data among the plurality of modules such that a unit of the data received from the bus is interleaved to only one of the plurality of modules.

14. The apparatus of claim 13, wherein the plurality of modules are configured to transfer the interleaved data to the register simultaneously.

15. The apparatus of claim 12, wherein the plurality of modules are each coupled to the register by a respective number of regions.

16. The apparatus of claim 15, wherein the number of regions comprises a number of regions greater than one, and wherein each of the plurality of modules is configured to transfer the interleaved data to the register in parallel by the respective number of regions.

17. The apparatus of claim 16, wherein each of the plurality of modules is configured to transfer one byte of the interleaved data per region per data cycle.

18. The apparatus of claim 17, wherein the apparatus is configured to output data from a particular memory cell in the plane of memory cells with a configurable data quantization.

19. The apparatus of claim 18, wherein the apparatus is configured to program the plane of memory cells with a configurable data density per memory cell.

20. The apparatus of claim 12, wherein the apparatus is configured to selectively disable the plurality of modules to transition from threshold voltage (Vt) placer mode to data placer mode.

21. The apparatus of claim 20, wherein Vt placer mode comprises programming a memory cell to a target programmed state directly, and wherein data placer mode comprises programming a memory cell to a target programmed state via a lower page programming operation and an upper page programming operation.

22. The apparatus of claim 20, wherein a data-path between the bus and the plane of memory cells for Vt placer mode is a same data-path as a data-path between the bus and the plane of memory cells for data placer mode.

23. An apparatus, comprising:

a bus coupled to a plurality of modules;

a register including a plurality of portions corresponding to the plurality of modules, wherein the register is coupled to the bus by the plurality of modules;

a plane of memory cells coupled to the register;

wherein each of the plurality of modules is configured to receive data from a respective one of the plurality of portions of the register;

wherein the apparatus is configured to deinterleave the data according to a selected one of a plurality of data densities per memory cell by transferring the data from each of the plurality of modules to the bus such that an amount of data corresponding to the selected data density is output from each of the plurality of modules.

24. The apparatus of claim 23, wherein each of the plurality of modules includes sensing circuitry and wherein each of the plurality of modules is configured to sense the data from the respective one of the plurality of portions of the register.

25. The apparatus of claim 23, wherein the apparatus is configured to selectively enable the plurality of modules to transition from data placer mode to threshold voltage (Vt) placer mode.

26. The apparatus of claim 25, wherein a data-path between the plane of memory cells and the bus for data placer mode is a same data-path as a data-path between the plane of memory cells and the bus for Vt placer mode.

27. The apparatus of claim 23, wherein the apparatus is configured to receive a signal indicating the selected one of the plurality of configured data densities per memory cell.

28. An apparatus, comprising:

a module controller coupled to;

a data scrambler to provide a connection to a bus; and

a number of regions to provide a connection to a register;

wherein the module controller is configured to;

receive a signal indicating a selected one of a plurality of data densities per memory cell;

cause the data scrambler to interleave amounts of data from the bus according to the selected data density; and

transfer the interleaved data via the plurality of regions.

29. The apparatus of claim 28, wherein the number of regions correspond 1:

1 to a number of bytes of data that can be transferred in parallel.

30. The apparatus of claim 28, wherein the module controller is configured to receive the signal indicating the configured data density from the bus.

31. The apparatus of claim 28, wherein the data scrambler is coupled to the number of regions via a data line driver, and wherein the module controller is configured to cause the data scrambler to send the interleaved data to the data line driver.

32. The apparatus of claim 31, wherein the module controller is configured to cause the data line driver to transfer respective portions of the interleaved data via each of the number of regions.

33. The apparatus of claim 28, wherein the module controller is configured to control different numbers of the number of regions according to different selected data densities.

34. The apparatus of claim 33, wherein the number of regions comprises four and wherein each region includes eight data lines.

35. An apparatus, comprising:

a module controller coupled to;

a data line scrambler coupled to a plurality of regions to provide a connection to a register; and

a data scrambler to provide a connection to a bus;

wherein the module controller is configured to;

cause the data line scrambler to receive data from the register via the plurality of regions; and

cause the data scrambler to deinterleave amounts of the data according to a selected one of a plurality of data densities per memory cell.

36. The apparatus of claim 35, wherein the module controller is coupled to sense circuitry;

and

wherein the sense circuitry is coupled between the data line scrambler and the data scrambler.

37. The apparatus of claim 36, wherein the module controller is configured to cause the sense circuitry to:

receive and sense the data received from the register via the plurality of regions; and

send the data to the data scrambler.

38. The apparatus of claim 35, wherein the module controller is configured to cause the data scrambler to transfer an amount of data corresponding to the selected data density to a bus during a plurality of clock cycles.

39. The apparatus of claim 38, wherein the module controller is configured to cause the data scrambler to transfer less than a clock cycle capacity amount of data to the bus during one of the plurality of clock cycles.

40. An apparatus, comprising:

a module controller coupled to additional circuitry to provide a connection to a register and to a bus;

wherein the module controller is configured to;

cause the additional circuitry to interleave amounts of data from the bus according to a selected one of a plurality of data densities per memory cell; and

cause the additional circuitry to deinterleave amounts of data from the register according to the selected data density.