Method and system for temporary data unit storage on infiniband host channel adaptor

• US 8,804,752 B2
• Filed: 05/31/2011
• Issued: 08/12/2014
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Manula, Brian Edward, Sandven, Magne Vigulf, Bugge, Haakon Ording
• Primary Examiner(s): Phillips, Hassan
• Assistant Examiner(s): FOUD, HICHAM B
• Application Number:
  US13/149,483
• Publication Number:
  US 20120307838A1
• Time in Patent Office: 1,169 Days
• Field of Search: None
• US Class Current: 370/412
• CPC Class Codes: H04L 49/358 Infiniband Switches

Abstract

A method for temporary storage of data units including receiving a first data unit to store in a hardware linked list queue on a communications adapter, reading a first index value from the first data unit, determining that the first index value does match an existing index value of a first linked list, and storing the first data unit in the hardware linked list queue as a member of the first linked list. The method further includes receiving a second data unit, reading a second index value from the second data unit, determining that the second index value does not match any existing index value, allocating space in the hardware linked list queue for a second linked list, and storing the second data unit in the second linked list.

Claims

1. A method for temporary storage of data units on a communications adapter, comprising:

receiving a first data unit to store in a hardware linked list queue on the communications adapter, wherein the hardware linked list queue comprises a plurality of linked lists;

reading a first index value from the first data unit;

determining that the first index value does match an existing index value of a first linked list of the plurality of linked lists, wherein the first linked list comprises a first plurality of data units;

storing the first data unit in the hardware linked list queue as a member of the first linked list;

receiving a second data unit to store in the hardware linked list queue on the communications adapter;

reading a second index value from the second data unit;

determining that the second index value does not match any existing index value of any of the plurality of linked lists stored in the hardware linked list queue;

allocating space in the hardware linked list queue for a second linked list to add the second linked list to the plurality of linked lists based on determining that the second index value does not match any existing index value;

storing the second data unit in the second linked list; and

for each transmission request of a plurality of transmission requests on the hardware linked list queue at least the following steps are performed;

identifying a list identifier in the transmission request;

identifying a head pointer of a requested linked list of the plurality of linked lists that matches the list identifier in the transmission request;

obtaining, from the hardware linked list queue, a requested data unit referenced by the head pointer; and

transmitting the requested data unit.

2. The method of claim 1, wherein storing the first data unit in the hardware linked list queue comprises:

identifying, using a free list, an available entry in the hardware linked list queue;

identifying, using a tail pointer, a previous tail entry in a data unit list,

storing, in the previous tail entry, a reference to a next tail entry in the data unit list, wherein the next tail entry corresponds to the available entry in the hardware linked list queue;

updating the tail pointer to reference the next tail entry; and

storing the first data unit in the available entry of the hardware linked list queue.

3. The method of claim 1, further comprising:

processing the first data unit in the hardware linked list queue; and

setting a data unit ready bit corresponding to the first data unit in response to completing processing of the first data unit,

wherein the data unit ready bit specifies that the first data unit is processed.

4. The method of claim 1, further comprising:

processing a head data unit in the first linked list from the hardware linked list queue;

setting a data unit ready bit corresponding to the head data unit in response to completing processing of the head data unit, wherein the data unit ready bit specifies that the head data unit is processed; and

setting a list ready bit corresponding to the first linked list based on the data unit ready bit being set, wherein the list ready bit specifies that the head data unit is ready for sending to a consumer module.

5. The method of claim 1, further comprising:

receiving a third data unit to store in the hardware linked list queue;

reading the third index value from the third data unit;

determining that an underlying function matching the third index value comprises a maximum allocated number of data units in the hardware linked list queue; and

dropping the third data unit based on the determination that the underlying function comprises the maximum allocated number of data units.

6. The method of claim 1, wherein the plurality of transmission requests comprises at least one selected from a group consisting of a pop command and a peek command.

7. The method of claim 1, further comprising:

receiving a flush command;

identifying a list identifier in the flush command; and

returning all entries of a requested linked list of the plurality of linked lists that matches the list identifier in the flush command to an available linked list for the hardware linked list queue.

8. A hardware linked list queue for temporary storage of data units on a communications adapter comprising:

a data list component comprising;

a data memory comprising a plurality of memory locations for storing a plurality of linked lists, wherein each linked list of the plurality of linked lists comprises at least one data unit;

a data list memory comprising;

a free list for storing a list of available memory locations in the data memory; and

a data unit list comprising a plurality of list entries, wherein each list entry of the plurality of list entries corresponds to a memory location of the plurality of memory locations, and wherein each list entry of the plurality of list entries stores an identifier of a next list entry in a same linked list; and

a data list controller for storing a head pointer for each list of the plurality of linked lists, wherein the head pointer references a first list entry in the data unit list; and

a management unit operatively connected to the data list component and configured to;

receive an inbound data unit; and

send the list identifier corresponding to the inbound data unit to the data list controller to associate the inbound data unit with the linked list corresponding to the inbound data unit,

wherein the data list component is configured, for each transmission request of a plurality of transmission requests, to perform at least the following;

identify a list identifier in the transmission request;

identify the head pointer of a requested linked list of the plurality of linked lists that matches the list identifier in the transmission request;

obtain, from the data memory, a requested data unit referenced by the head pointer; and

transmit the requested data unit.

9. The hardware linked list queue of claim 8, further comprising:

a data unit ready component for storing a data unit ready bit string comprising a first plurality of bits, wherein each bit of the first plurality of bits corresponds to a distinct list entry in the data unit list, and wherein each bit of the first plurality of bits identifies whether processing is completed on a data unit corresponding to the distinct list entry.

10. The hardware linked list queue of claim 9, further comprising:

a list ready component for storing a list ready bit string comprising a second plurality of bits, wherein each bit of the second plurality of bits corresponds to a distinct linked list of the plurality of linked lists, and wherein each bit of the second plurality of bits identifies whether processing is completed on a data unit corresponding to a first data unit of the distinct linked list.

11. The hardware linked list queue of claim 8, wherein communications adapter is a host channel adapter.

12. The hardware linked list queue of claim 8, further comprising:

a list identifier to index memory configured to store a mapping between list identifiers and index values.

13. The hardware linked list queue of claim 8, further comprising:

index to list identifier memory configured to store a mapping between index values and list identifiers.

14. The hardware linked list queue of claim 8, further comprising:

an inbound credit storage configured to store a number of available entries in the free list.

15. The hardware linked list queue of claim 8, wherein the management component is further configured to send an entry unique identifier for the at least one data unit to a data unit processor, and wherein the data unit processor processes the at least one data unit.

16. The hardware linked list queue of claim 8, wherein the plurality of transmission requests are received from an arbitrator, wherein the arbitrator selects the requested linked list for transmitting the requested data unit.

17. A communications adapter comprising:

a producer module;

a consumer module; and

a current module interposed between the producer module and the consumer module and configured to;

receive, from the producer module, a first data unit to store in a hardware linked list queue on the communications adapter, wherein the hardware linked list queue comprises a plurality of linked lists;

read a first index value from the first data unit;

determine that the first index value does match an existing index value of a first linked list of the plurality of linked lists, wherein the first linked list comprises a first plurality of data units;

store the first data unit in the hardware linked list queue as a member of the first linked list;

receive, from the producer module, a second data unit to store in the hardware linked list queue on the communications adapter;

read a second index value from the second data unit;

determine that the second index value does not match any existing index value of any of the plurality of linked lists stored in the hardware linked list queue;

allocate space in the hardware linked list queue for a second linked list to add the second linked list to the plurality of linked lists based on determining that the second index value does not match any existing index value;

store the second data unit in the second linked list; and

for each transmission request of a plurality of transmission requests on the hardware linked list queue at least the following steps are performed;

identify a list identifier in the transmission request;

identify a head pointer of a requested linked list of the plurality of linked lists that matches the list identifier in the transmission request;

obtain, from the hardware linked list queue, a requested data unit referenced by the head pointer; and

transmit, to the consumer module, the requested data unit.

18. The communications adapter of claim 17, wherein the communications adapter is a host channel adapter, and wherein the producer module, the current module, and the consumer module are each one selected from a group consisting of a collect buffer unit module, a virtual kick module, a queue pair fetch module, a DMA module, a packet builder module, a completion module, a packet receiver module, a receive module, a descriptor fetch module, a receive queue entry handler module, and a DMA validation module.

19. The communications adapter of claim 17, wherein the communications adapter is a host channel adapter, and wherein the host channel adapter comprises a collect buffer unit module, a virtual kick module, a queue pair fetch module, a DMA module, a packet builder module, a completion module, a packet receiver module, a receive module, a descriptor fetch module, a receive queue entry handler module, and a DMA validation module.

20. The communications adapter of claim 19, wherein the collect buffer unit module, the virtual kick module, the queue pair fetch module, the DMA module, the packet builder module, the completion module, the packet receiver module, the receive module, the descriptor fetch module, the receive queue entry handler module, and the DMA validation module each comprise a separate hardware linked list queue.