Modulation agnostic digital hybrid mode power amplifier system and method

• US 8,804,870 B2
• Filed: 12/21/2010
• Issued: 08/12/2014
• Est. Priority Date: 12/21/2009
• Status: Active Grant

• Current Assignee: Dali Systems Co., Ltd.
• Original Assignee: Dali Systems Co., Ltd.
• Inventors: Kim, Wan Jong, Cho, Kyoung Joon, Stapleton, Shawn Patrick, Xiao, Ying
• Primary Examiner(s): Burd, Kevin M
• Application Number:
  US12/928,931
• Publication Number:
  US 20110156815A1
• Time in Patent Office: 1,330 Days
• Field of Search: 375/295, 375/296, 375/297
• US Class Current: 375/297
• CPC Class Codes: H03F 1/304 and using digital means
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3258 based on polynomial terms
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/204 A hybrid coupler being used at the output of an amplifier circuit
• CPC Class Codes: H03F 2200/207 A hybrid coupler being used as power measuring circuit at the output of an amplifier circuit
• CPC Class Codes: H03F 2200/447 the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2201/3206 Multiple channels are combined and amplified by only one amplifier
• CPC Class Codes: H03F 2201/3209 the amplifier comprising means for compensating memory effects
• CPC Class Codes: H03F 2201/3212 Using a control circuit to adjust amplitude and phase of a signal in a signal path
• CPC Class Codes: H03F 2201/3215 To increase the output power or efficiency
• CPC Class Codes: H03F 2201/3224 Predistortion being done for compensating memory effects
• CPC Class Codes: H03F 2201/3227 Adaptive predistortion based on amplitude, envelope or power level feedback from the output of the main amplifier
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/067 providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/0008 : arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453
• CPC Class Codes: H04L 27/368 : adaptive predistortion
• CPC Class Codes: H04W 24/02 : Arrangements for optimising operational condition

Abstract

A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.

Claims

1. A digital predistortion system for linearizing the output of power amplifiers comprising:

input signal suitable for wireless communications,

at least one power amplifier for outputting an amplified signal,

at least one feedback signal derived from the amplified signal including a representation of a noise characteristic of the at least one power amplifier, estimator logic responsive to the at least one feedback signal for generating predistortion coefficients based at least in part on feedback path delay determined from the correlation given by the equation

2. The digital predistortion system of claim 1 configured for base station applications further comprising a digital field programmable gate array that includes one or more of a digital up-converter, a crest factor reduction, a predistorter, or a digital quadrature modulator.

3. The digital predistortion system of claim 1 configured for repeater applications further comprising a digital field programmable gate array that includes at least one of a digital quadrature demodulator, a crest factor reduction, a predistorter, or a digital quadrature modulator.

4. The digital predistortion system of claim 1 further comprising a digital field programmable gate array that provides predistortion that compensates adaptively for both nonlinearity and memory effects by generating asymmetric distortion of the power amplifier.

5. The digital predistortion system of claim 1 further comprising a digital field programmable gate array that includes an adaptation algorithm to determine the optimum gate bias voltage of the power amplifier for stabilizing the linearity fluctuations due to the temperature changes of the power amplifier.

6. The digital predistortion system of claim 1 wherein the power amplifier portion uses at least one of the following efficiency boosting techniques:

Doherty, Envelope Elimination and Restoration, Envelope Tracking, Envelope Following, or Linear amplification using Nonlinear Components in order to maximize the efficiency of the power amplifier system.