Digital signal processing circuitry with redundancy and bidirectional data paths

• US 8,805,916 B2
• Filed: 03/03/2009
• Issued: 08/12/2014
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin, Lin, Yi-Wen, Streicher, Keone
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US12/380,841
• Publication Number:
  US 20100228807A1
• Time in Patent Office: 1,988 Days
• Field of Search: 326 37- 47, 708/490, 708/523, 708/603, 708620-625
• US Class Current: 708/523
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08

Abstract

Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).

Claims

1. A digital signal processing (“

DSP”

) circuit block comprising;

first and second N-bit multiplier circuits;

first shifter circuitry for shifting outputs of the first multiplier circuit by a selectable one of (1) zero bit positions and (2) N bit positions toward greater arithmetic significance;

first compressor circuitry for additively combining outputs of the first shifter circuitry and the second multiplier circuit;

circuitry for selectively routing outputs of the first compressor circuitry to first and second other DSP circuit blocks that are on respective opposite sides of the DSP circuit block;

second shifter circuitry for shifting outputs of the first compressor circuitry by a selectable one of (1) zero bit positions, (2) N bit positions toward greater arithmetic significance, and (3) N bit positions toward lesser arithmetic significance; and

second compressor circuitry for additively combining outputs of the second shifter circuitry and any outputs received from the first compressor circuitry in either of the first and second other DSP circuit blocks.

2. The DSP circuit block defined in claim 1 wherein the routing circuitry is controllable to select for routing any one of a plurality of subsets of the outputs of the first compressor circuitry.

3. The DSP circuit block defined in claim 2 wherein the selectable subsets include (1) a subset including a most significant output bit position of the first compressor circuitry, and (2) a subset including a least significant output bit position of the first compressor circuitry.

4. The DSP circuit block defined in claim 1 wherein the second compressor circuitry comprises:

overflow output circuitry for applying overflow output signals of the second compressor circuitry to the first other DSP circuit block; and

overflow input circuitry for selectively receiving overflow output signals of the second compressor circuitry in the second other DSP circuit block.

5. The DSP circuit block defined in claim 1 further comprising:

third compressor circuitry for additively combining outputs of the second compressor circuitry and any further outputs received from the second other DSP circuit block; and

further routing circuitry for selectively routing outputs of the third compressor circuitry, as further outputs, to the first other DSP circuit block.

6. The DSP circuit block defined in claim 5 wherein the further routing circuitry is alternatively able to output data that is all zeros.

7. The DSP circuit block defined in claim 5 wherein the third compressor circuitry comprises:

overflow output circuitry for applying overflow output signals of the third compressor circuitry to the first other DSP circuit block; and

overflow input circuitry for selectively receiving overflow output signals of the third compressor circuitry in the second other DSP circuit block.

8. The DSP circuit block defined in claim 5 wherein the further routing circuitry comprises:

carry-propagate adder (“

CPA”

) circuitry for operating on the outputs of the third compressor circuitry to produce the further outputs.

9. The DSP circuit block defined in claim 8 wherein the CPA circuitry comprises:

carry-out circuitry for applying a carry out signal of the CPA circuitry to the first other DSP circuit block; and

carry-in circuitry for selectively receiving a carry out signal of the CPA circuitry in the second other DSP circuit block.

10. The DSP circuit block defined in claim 1 wherein each of the first and second multiplier circuits can multiply an N-bit multiplicand by an N-bit multiplier.

11. The DSP circuit block defined in claim 10 wherein N is equal to 18.

12. The DSP circuit block defined in claim 1 further comprising:

redundancy circuitry for allowing the first other DSP circuit block to be a selectable one of (1) another DSP circuit block that is immediately adjacent to the DSP circuit block, and (2) yet another DSP circuit block that is not immediately adjacent to the DSP circuit block.

13. The DSP circuit block defined in claim 12 wherein the yet another DSP circuit block is immediately adjacent to the another DSP circuit block.

14. The DSP circuit block defined in claim 12 further comprising:

further redundancy circuitry for allowing the second other DSP circuit block to be a selectable one of (1) still another DSP circuit block that is immediately adjacent to the DSP circuit block, and (2) still a further other DSP circuit block that is not immediately adjacent to the DSP circuit block.

15. The DSP circuit block defined in claim 14 wherein the still a further other DSP circuit block is immediately adjacent to the still another DSP circuit block.

16. The DSP circuit block defined in claim 1 wherein the first shifter circuitry is alternatively able to output data that is all zeros.

17. The DSP circuit block defined in claim 1 wherein the second shifter circuitry is alternatively able to output data that is all zeros.

18. The DSP circuit block defined in claim 1 wherein the circuitry for selectively routing is alternatively able to output data that is all zeros.

19. Digital signal processing (“

DSP”

) circuitry in an integrated circuit device, said circuitry comprising;

a plurality of DSP circuit blocks, each of which is capable of performing DSP operations on signals applied to that DSP circuit block, each of the DSP circuit blocks including;

a plurality of components, each for performing a respective arithmetic operation as part of DSP operations; and

circuitry, separate from general-purpose interconnect of said integrated circuit device, for selectively routing outputs of a plurality of individual ones of the plurality of components directly to components of first and second other ones of the DSP circuit blocks, that are on respective opposite sides of that DSP circuit block, without using said general-purpose interconnect for said routing, wherein the circuitry for selectively routing of each of the DSP circuit blocks comprises;

redundancy circuitry, separate from said general-purpose interconnect, for allowing selection of the first other DSP circuit block for that DSP circuit block from among both (1) another DSP circuit block that is immediately adjacent to that DSP circuit block, and (2) yet another DSP circuit block that is not immediately adjacent to that DSP circuit block.

20. The DSP circuitry defined in claim 19 wherein the yet another DSP circuit block is immediately adjacent to the another DSP circuit block.

21. The DSP circuitry defined in claim 19 wherein the circuitry for selectively routing of each of the DSP circuit blocks further comprises:

further redundancy circuitry, separate from said general-purpose interconnect, for allowing selection of the second other DSP circuit block for that DSP circuit block from among both (1) still another DSP circuit block that is immediately adjacent to that DSP circuit block, and (2) still a further other DSP circuit block that is not immediately adjacent to that DSP circuit block.

22. The DSP circuitry defined in claim 21 wherein the still a further other DSP circuit block is immediately adjacent to the still another DSP circuit block.

23. The DSP circuitry defined in claim 19 wherein the circuitry for selectively routing of each of the DSP circuit blocks selectively routes the outputs to inputs of components of the first and second other ones of the DSP circuit blocks that are downstream from some but not all components of the first and second other ones of the DSP circuit blocks that are capable of performing arithmetic operations.

24. The DSP circuitry defined in claim 19 wherein each of the DSP circuit blocks is disposed in a respective one of a plurality of rows which also includes other circuitry, the other circuitry in each of the rows having a maximum width W between other adjacent rows, and the DSP circuit blocks in each of the rows also having a maximum width W between the other adjacent rows.

25. Digital signal processing (“

DSP”

) circuitry in an integrated circuit device, said circuitry comprising;

a plurality of DSP circuit blocks including a plurality of components, each of which is capable of performing, one after another in succession, a plurality of arithmetic operations as part of DSP operations, each of the DSP circuit blocks including circuitry, separate from general-purpose interconnect of said integrated circuit device, for selectively routing outputs of a plurality of individual ones of the plurality of components of that DSP circuit block to first and second other ones of the DSP circuit blocks that are on respective opposite sides of that DSP circuit block, without using said general-purpose interconnect for said routing, wherein the circuitry for selectively routing of each DSP circuit block selectively routes at least some of the outputs directly to inputs of components in the first and second other DSP circuit blocks that are intermediate in the succession of components in those other DSP circuit blocks; and

redundancy circuitry, separate from general-purpose interconnect, for allowing selection of the first other DSP circuit block for each of the DSP circuit blocks from among both (1) another of the DSP circuit blocks that is immediately adjacent to the DSP circuit block, and (2) yet another of the DSP circuit blocks that is not immediately adjacent to the DSP circuit block.

26. The DSP circuitry defined in claim 25 wherein at least some of the inputs are inputs to components at a different point in the succession in the other DSP circuit blocks than the point in the succession of components in the DSP circuit block from which the circuitry for selectively routing received the outputs selectively routed to those at least some inputs.

27. The DSP circuitry defined in claim 26 wherein each of the DSP circuit blocks further comprises:

second circuitry for selectively routing a second output of a component in that DSP circuit block to an input of a same component in the first other DSP circuit block.

28. The DSP circuitry defined in claim 27, wherein each of the DSP circuit blocks further comprises:

third circuitry, separate from said general-purpose interconnect, for selectively routing outputs of a final arithmetic operation in that DSP circuit block to inputs to a component in the first other DSP circuit block that is at an intermediate point in the succession of components in that other DSP circuit block, without using said general-purpose interconnect for said routing.

29. The DSP circuitry defined in claim 25 wherein the yet another of the DSP circuit blocks is immediately adjacent to the another of the DSP circuit blocks.

30. The DSP circuitry defined in claim 25 further comprising:

further redundancy circuitry, separate from said general-purpose interconnect, for allowing selection of the second other DSP circuit block of each of the DSP circuit blocks from among both (1) still another of the DSP circuit blocks that is immediately adjacent to the DSP circuit block, and (2) still a further another one of the DSP circuit blocks that is not immediately adjacent to the DSP circuit block.

31. The DSP circuitry defined in claim 30 wherein the still a further another one of the DSP circuit blocks is immediately adjacent to the still another of the DSP circuit blocks.