Flexible memory protection and translation unit

• US 8,806,110 B2
• Filed: 09/21/2011
• Issued: 08/12/2014
• Est. Priority Date: 09/21/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zbiciak, Joseph R. M., Menon, Amitabh, Anderson, Timothy D.
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US13/239,063
• Publication Number:
  US 20120191899A1
• Time in Patent Office: 1,056 Days
• Field of Search: 711/103, 711/163, 711/E12.093, 726/26
• US Class Current: 711/103
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 13/366 using a centralised polling arbiter
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.

Claims

1. A memory management system comprising:

a memory organized as a plurality of programmable memory segments, said memory segments having a strict priority,

a plurality of requestors operable to originate memory access requests wherein the request includes a logical memory address to be accessed, a descriptor of the requested access and a permission field containing a plurality of bits indicating the access permissions associated with the request,

an extended memory controller connected to said plural memory segments of said memory and to said plural requestors operable to control access to said memory, said extended memory controller including

a segment register associated with each memory segment operable to store parameter fields defining the memory segment including a set of upper bits of a memory starting address, memory size and a plurality of permission bits, and a set of replacement address bits,

a comparison circuit operable to compare the memory address range in the segment registers as defined by the upper bits of the starting address and memory size of each segment register, and the logical memory address provided as part of the memory access request provided by the requestor, and further operable to select a segment register corresponding to a memory section having the highest priority having the requested address is within said memory address range of the selected segment register, and

a logic circuit granting a memory access request if said plurality of permission bits of said selected segment register permit access to said access permissions associated with said request, said logic circuit generating an access address by replacing said upper bits of said logical memory address with said replacement address bits while retaining lower bits of said logical memory address of said memory access request.

2. The memory management system of claim 1, wherein:

the size of the memory segments are expressed as a power of 2.

3. The memory management system of claim 1, wherein:

the access permissions and priorities of each memory segment is programmable.

4. The extended memory controller of claim 1, wherein:

the replacement bits stored in each segment register include more bits than said upper bits of said memory starting address stored in the same segment register.