Mounted cache memory in a multi-core processor (MCP)

• US 8,806,129 B2
• Filed: 11/21/2008
• Issued: 08/12/2014
• Est. Priority Date: 11/21/2008
• Status: Expired due to Fees

• Current Assignee: Kyndryl Incorporated (Kyndryl Holdings, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Duvalsaint, Karl J., Kim, Daeik, Kim, Moon J.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/275,508
• Publication Number:
  US 20100131713A1
• Time in Patent Office: 2,090 Days
• Field of Search: 711/130, 711/117, 711/118, 711/148, 709/213
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system. It should be understood in advance the teachings herein are typically applied to a Multi-Core Processor (MCP), although this need not be the case.

Claims

1. A mounted memory system, comprising:

a first memory unit mounted on a bus;

a first cache manager coupled to an input and an output of the first memory unit;

a second memory unit mounted on the bus;

a second cache manager coupled to an input and an output of the second memory unit, the first memory unit and the second memory unit being adapted to receive and send communications via the first cache manager and the second cache manager;

a second set of sub-memory units and a second set of sub-processing elements coupled to the second cache manager, the second set of sub-memory units and the second set of sub-processing elements located on a lower hierarchical level than the second memory unit; and

wherein the second cache manager is configured to receive a request for memory content from the first cache manager and direct the request for memory content to the input of the second memory unit to enable the second memory unit to function as a next-level higher cache to the first memory unit, including in the case that either of the following are non-operational;

the second set of sub-memory units, and the second set of sub-processing elements.

2. The mounted memory system of claim 1, the first memory unit and the second memory unit comprising virtualized cache memory units.

3. The mounted memory system of claim 1, further comprising:

a first set of sub-memory units coupled to the first cache manager; and

a first set of sub-processing elements coupled to the first set of sub-memory units.

4. The mounted memory system of claim 3, the first memory unit being adapted to receive a request from any of the first set of sub-memory units via the first cache manager.

5. The mounted memory system of claim 4, the first memory unit being further adapted to forward the request to the second memory unit via the first cache manager and the second cache manager.

6. The mounted memory system of claim 1, the second memory unit being adapted to receive a request from any of the second set of sub-memory units via the second cache manager.

7. The mounted memory system of claim 6, the second memory unit being further adapted to forward the request to the first memory unit via the second cache manager and the first cache manager.

8. The mounted memory system of claim 1, the bus being coupled to a main controller.

9. A mounted cache system, comprising:

a first cache memory unit mounted on a bus;

a first cache manager coupled to an input and an output of the first cache memory unit;

a first set of sub-cache memory units and a first set of sub-processing elements coupled to the first cache manager, the first set of sub-cache memory units and the first set of sub-processing elements located on a lower hierarchical level than the first cache memory unit;

a second cache memory unit mounted on the bus;

a second cache manager coupled to an input and an output of the second cache memory unit; and

a second set of sub-cache memory units coupled to the second cache manager and located on a lower hierarchical level than the second cache memory unit, the first cache memory unit and the second cache memory unit being adapted to receive and send communications via the first cache manager and the second cache manager, and wherein the second cache manager is configured to receive a request for memory content originating from the first set of sub-processing elements coupled to the first set of sub-cache memory units via the first cache manager and direct the request for memory content to the input of the second memory unit to enable the second memory unit to function as a next-level higher cache to the first memory unit, including in the case that the second set of sub-cache memory units is non-operational.

10. The mounted cache system of claim 9, the first cache memory unit being adapted to receive a request from any of the first set of sub-cache memory units via the first cache manager.

11. The mounted cache system of claim 10, the first cache memory unit being further adapted to forward the request to the second cache memory unit via the first cache manager and the second cache manager.

12. The mounted cache system of claim 9, further comprising a second set of sub-processing elements coupled to the second set of sub-cache memory units.

13. The mounted cache system of claim 12, the second cache memory unit being adapted to receive a request from any of the second set of sub-cache memory units via the second cache manager.

14. The mounted cache system of claim 13, the second cache memory unit being further adapted to forward the request to the first cache memory unit via the second cache manager and the first cache manager.

15. The mounted cache system of claim 9, the bus being coupled to a main controller.

16. A mounted cache memory method, comprising:

issuing a first request for memory content originating from a first set of sub-processing elements coupled to a first cache memory unit that is coupled to a bus, the first request for memory content being received by the first cache memory unit via a first cache manager coupled to an input and an output of the first cache memory unit, and the first set of sub-processing elements being located on a lower hierarchical level than the first cache memory unit; and

issuing, including in the case that a second set of sub-cache memory units of coupled to a second cache memory unit is non-operational, a second request for the memory content from the first cache memory unit to the second cache memory unit that is coupled to the bus, the second request being received at an input of the second cache memory unit via a second cache manager coupled to the input and an output of the second cache memory unit to enable the second memory unit to function as a next-level higher cache to the first memory unit, and wherein the second set of sub-cache memory units is located on a lower hierarchical level than the second memory unit.

17. The mounted cache memory method of claim 16, the first request being received from a first set of sub-cache memory units coupled to the first cache memory unit.

18. The mounted cache memory method of claim 16, the second request being issued pursuant to a failure by the first cache memory unit to fulfill the first search request, and wherein an additional request to at least one externally located cache memory unit is issued by each of the first cache memory unit and the second memory unit pursuant to a failure by the second cache memory unit to fulfill the second search request.