Porting a circuit design from a first semiconductor process to a second semiconductor process

• US 8,806,395 B1
• Filed: 02/03/2014
• Issued: 08/12/2014
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T., Thompson, Scott E., Roy, Richard S., Leshner, Samuel
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US14/171,224
• Time in Patent Office: 190 Days
• Field of Search: 716/51, 716/52, 716/54
• US Class Current: 716/54
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

Claims

1. A method of fabricating an integrated circuit including a bit cell comprising:

determining a size of each transistor in a first bit cell design, each of the transistors having a threshold voltage;

producing a second bit cell design based on the first bit cell design, the second bit cell design having target transistors, the target transistors including at least one deeply depleted channel (DDC) transistor, the second bit cell design having initial threshold voltage value assigned to each of the target transistors;

determining targets for a read margin, a write margin, a read current and a cell leakage for the second bit cell, such targets defining set of design constraints;

optimizing the threshold voltage values of the target transistors using an optimization method based upon solving objective functions within the set of design constraints;

selectively doping a semiconductor substrate to form a highly-doped screening region over which a transistor gate will be formed;

selectively doping the semiconductor substrate in regions that are associated with the target transistors to dopant concentrations that set the threshold voltage values for each of the target transistors to the desired range of values; and

forming a substantially undoped semiconductor layer above the highly doped screening region.

2. The method of claim 1, wherein the second bit cell has a width and a length.

3. The method of claim 2, further comprising determining targets for the width and length of the second bit cell.

4. The method of claim 3, wherein optimizing the threshold voltage values comprises optimizing at least one of the width, or the length of the DDC transistor.

5. The method of claim 4, wherein selectively doping the target transistors comprises using a mask pattern that is designed based upon the optimized width and length of the DDC transistor.

6. The method of claim 1, wherein the bit cell is a 6-T SRAM.

7. The method of claim 1, wherein the step of forming a substantially undoped semiconductor layer comprises growing a silicon epitaxial layer.

8. The method of claim 1, wherein the DDC transistor is an n-channel transistor.

9. The method of claim 1, wherein the DDC transistor is a p-channel transistor.

10. The method of claim 1, further comprising forming source/drain extension regions above the highly-doped screening region.

11. A method of fabricating an integrated circuit including a bit cell having a read margin, write margin, read current and cell leakage, wherein the bit cell was initially designed for a first semiconductor process, wherein such bit cell is to be migrated to a second semiconductor process, the method comprising:

determining the size of transistors in the initially designed bit cell, each of the transistors having a threshold voltage;

providing a design for the migrated bit cell having target transistors, the target transistors each having a channel, and having specifications for threshold voltages which can be implemented by introducing dopants into the channels;

selecting initial values of the threshold voltages of each of the target transistors;

determining targets for read margin, write margin, read current and cell leakage for the migrated bit cell, such targets defining a set of design constraints;

optimizing the threshold voltage values of the target transistors using an optimization method based upon solving objective functions within the set of design constraints; and

selectively doping the target transistors to dopant concentrations that are associated with achieving the threshold voltage values for each of the target transistors.

12. The method of claim 11, wherein the migrated bit cell has a width and a length.

13. The method of claim 12, further comprising determining targets for the width and length of the migrated bit cell.

14. The method of claim 13, wherein optimizing the threshold voltage values comprises optimizing the width and length of a target transistor.

15. The method of claim 11, wherein at least one of the target transistors is an n-channel DDC transistor.

16. The method of claim 11, wherein at least one of the target transistors is a p-channel DDC transistor.

17. The method of claim 15, further comprising:

forming a highly-doped screening region in the p-channel DDC transistor.

18. The method of claim 16, further comprising:

forming a highly-doped screening region in the p-channel DDC transistor.

19. The method of claim 17, further comprising:

forming source/drain extension regions above the highly-doped screening region.

20. The method of claim 18, further comprising:

forming source/drain extension regions above the highly-doped screening region.