Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby

• US 8,806,408 B2
• Filed: 02/03/2009
• Issued: 08/12/2014
• Est. Priority Date: 05/07/2008
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Parker, James C., Rao, Vishwas M., Schneider, Clayton E. Jr., Sheets, Gregory W., Subbarao, Prasad
• Primary Examiner(s): TAT, BINH C
• Application Number:
  US12/364,918
• Publication Number:
  US 20100026378A1
• Time in Patent Office: 2,016 Days
• Field of Search: 716132-136
• US Class Current: 716/132
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.

Claims

1. A method of designing an integrated circuit, comprising:

generating a functional design for said integrated circuit;

determining performance objectives for said integrated circuit;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, selecting between employing static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives, wherein said using is performed by a processor

determining a routing at said optimization target voltage;

implementing a layouy of said integrated circuit from said netlist; and

performing a timing signoff of said layout at said optimization target voltage.

2. The method as recited in claim 1 wherein said performance objectives include one selected from the group consisting of:

a target power consumption,

a target area, and

a target speed.

3. The method as recited in claim 1 wherein said using comprises:

synthesizing a clock tree for said integrated circuit; and

determining a routing at said optimization target voltage.

4. The method as recited in claim 1 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology.

5. The method as recited in claim 1 wherein said adaptive voltage scaling is capable of being carried out without software control.

6. The method as recited in claim 1 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.

7. A method of designing an integrated circuit, comprising:

generating a functional design for said integrated circuit;

determining performance objectives for said integrated circuit, said performance objectives including one selected from the group consisting of;

a target power consumption,

a target area, and

a target speed;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, selecting between employing static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives and a clock tree for said integrated circuit, wherein said using is performed by a processor;

determining a routing at said optimization target voltage;

implementing a layout of said integrated circuit from said netlist; and

performing a timing signoff of said layout at said optimization target voltage.

8. The method as recited in claim 7 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology.

9. The method as recited in claim 7 wherein said adaptive voltage scaling is capable of being carried out without software control.

10. The method as recited in claim 7 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.

11. A computer program product, comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method of designing an integrated circuit, said method comprising:

generating a functional design for said integrated circuit;

determining performance objectives for said integrated circuit;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, selecting between employing static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives

determining a routing at said optimization target voltage;

implementing a layout of said integrated circuit from said netlist; and

performing a timing signoff of said layout at said optimization target voltage.

12. The computer program product as recited in claim 11 wherein said performance objectives include one selected from the group consisting of:

a target power consumption,

a target area, and

a target speed.

13. The computer program product as recited in claim 11 wherein said using comprises:

synthesizing a clock tree for said integrated circuit; and

determining a routing at said optimization target voltage.

14. The computer program product as recited in claim 11 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology.

15. The computer program product as recited in claim 11 wherein said adaptive voltage scaling is capable of being carried out without software control.

16. The computer program product as recited in claim 11 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.

17. A computer program product, comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method of designing an integrated circuit, said method comprising:

generating a functional design for said integrated circuit;

determining performance objectives for said integrated circuit, said performance objectives including one selected from the group consisting of;

a target power consumption,

a target area, and

a target speed;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, selecting between employing static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives and a clock tree for said integrated circuit;

determining a routing at said optimization target voltage;

implementing a layout of said integrated circuit from said netlist; and

performing a timing signoff of said layout at said optimization target voltage.

18. The computer program product as recited in claim 17 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology.

19. The computer program product as recited in claim 17 wherein said adaptive voltage scaling is capable of being carried out without software control.

20. The computer program product as recited in claim 17 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.