Apparatus and methods for de-embedding through substrate vias

• US 8,809,073 B2
• Filed: 08/03/2011
• Issued: 08/19/2014
• Est. Priority Date: 08/03/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Lin, Yu-Ling, Kuo, Chin-Wei, Chang, Victor Chih Yuan, Jeng, Min-Chie
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US13/197,602
• Publication Number:
  US 20130032799A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/48, 257/774, 438/14, 438 17- 18, 702/117, 702/119, 702/123, 324/525, 324/527, 324/756.01, 324/756.02, 324/756.05, 324/762.01, 324/750.16
• US Class Current: 438/14
• CPC Class Codes: G01R 31/2644 Adaptations of individual semiconductor devices to facilitate the testing thereof
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

Claims

1. A method, comprising:

providing a through substrate via (“

TSV”

) device under test extending through and disposed on a substrate;

providing a plurality of surrounding TSVs around the device under test on the substrate;

coupling a signal to the TSV device under test on a front side of the substrate;

providing a back side metal coupling the TSV device under test and the surrounding TSVs at the back side of the substrate;

providing a dummy structure equal in area to the back side metal area of the back side metal;

supplying a signal to TSV device under test; and

receiving the signal through the surrounding TSVs coupled in parallel.

2. The method of claim 1, wherein a resistance of the TSV device under test is determined by making a measurement of the resistance of the signal through the TSV device under test, the backside metal, and the surrounding TSVs;

and

subtracting the resistance due to the dummy structure.

3. The method of claim 1, wherein the TSV device under test and the surrounding TSVs each are lined with a dielectric and each forms a capacitance from TSV to substrate and the capacitance is further measured by:

coupling a positive voltage bias to the TSV device under test;

coupling a negative voltage bias to the surrounding TSVs in parallel; and

measuring the total capacitance, the capacitance for the TSV device under test approximately equal to the total capacitance when the number of surrounding TSVs is greater than 10.

4. The method of claim 1 wherein the substrate is floating.

5. The method of claim 4, further comprising providing a MOM or MIM capacitor between the TSV device under test and the substrate.

6. A method, comprising:

providing on a substrate having at least two through substrate vias (“

TSVs”

) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs;

measuring the intrinsic characteristics [L] for a first test structure on the substrate including two pads coupled with a transmission line of length L;

measuring the intrinsic characteristics [LX] of a second test structure on the substrate including two pads coupled with a transmission line of length L*X, where X is greater than 1;

measuring the intrinsic characteristics [BM_L] of a third test structure on the substrate including a first metal line of length [L] and at least two TSVs;

measuring the intrinsic characteristics [BM_LX] of a fourth test structure on the substrate including a second metal line of length L*X and at least two TSVs;

using simultaneous solutions of ABCD matrix or T matrix form equations for L and LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines;

de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and

using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs and the metal lines.

7. The method of claim 6, wherein the intrinsic characteristics of the pads and the transmission lines are used to de-embed the parasitic values from a resistance measurement of two TSVs and a metal line;

and

extrapolation is used to determine the resistance of two TSVs.

8. The method of claim 7, and further comprising:

measuring the intrinsic characteristics of a device under test comprising a first pad coupled by a first transmission line on a first surface of the substrate to a first TSV, a metal line formed on a second opposite surface of the substrate, a second TSV, a second transmission line formed on the first surface of the substrate, and a second pad; and

de-embedding the parasitic values due to the first pad, the first transmission line, the second pad, the second transmission line, and the metal line, to extract the intrinsic characteristics of the two TSVs.

9. The method of claim 7, wherein measuring the intrinsic characteristics comprises performing a ground signal ground RF probe at a wafer test station.

10. The method of claim 7, wherein providing a substrate further comprises providing a substrate including active transistor devices formed upon the substrate.

11. The method of claim 7, wherein providing a substrate further comprises providing an interposer substrate free from active transistor devices.