Fabrication of MOS device with schottky barrier controlling layer

• US 8,809,143 B2
• Filed: 12/21/2012
• Issued: 08/19/2014
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin, Pan, Ji, Wei, Sung-Po
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/725,789
• Publication Number:
  US 20130203225A1
• Time in Patent Office: 606 Days
• Field of Search: 438/237, 438/259
• US Class Current: 438/237
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a gate trench in an epitaxial layer overlaying a semiconductor substrate;

depositing gate material in the gate trench;

forming a body;

forming a source;

forming an active region contact trench that extends through the source and the body into a drain;

forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench, wherein the Schottky barrier controlling layer does not extend substantially into the body; and

disposing a contact electrode within the active region contact trench.

2. The method of claim 1, wherein forming the Schottky barrier controlling layer includes depositing a layer of material doped with opposite polarity dopant as the epitaxial layer in the epitaxial layer in the bottom region of the active region contact trench.

3. The method of claim 1, wherein the gate trench is a first gate trench;

and

the method further comprising forming a gate region, including by;

forming a second gate trench extending into the epitaxial layer;

forming a second gate disposed in the second gate trench; and

forming a gate contact trench formed within the second gate.

4. The method of claim 3, wherein the gate contact trench and the active region contact trench have approximately the same depth.

5. The method of claim 1, further comprising depositing a blanket implant deposited throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer.

6. The method of claim 1, further comprising forming an epitaxial layer profile tuning implant deposited under the active region contact trench.

7. The method of claim 1, further comprising forming an island region below the active region contact trench, wherein the island region has opposite polarity as the epitaxial layer.

8. The method of claim 1, wherein the gate material is formed to extend above the body top surface.