Fabricating method of trench-gate metal oxide semiconductor device

• US 8,809,163 B2
• Filed: 12/03/2013
• Issued: 08/19/2014
• Est. Priority Date: 08/09/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liu, Kuan-Ling, Ueng, Shih-Yuan
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US14/095,988
• Publication Number:
  US 20140094013A1
• Time in Patent Office: 259 Days
• Field of Search: 257/330, 257/342, 257/E21.41, 257/E29.262, 257/331, 438/270, 438/386, 438/431, 438/488, 438/430
• US Class Current: 438/430
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]

Abstract

A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Claims

1. A fabricating method of a trench-gate metal oxide semiconductor device, the fabricating method comprising steps of:

defining a first zone and a second zone in a substrate;

forming at least one first trench in the substrate in the second zone;

forming a dielectric layer on the first zone and the second zone, and filling the dielectric layer in the first trench;

performing an etching process to form at least one second trench in the substrate in the first zone by using the dielectric layer as a whole as an etching mask to remove a portion of the substrate;

forming a first gate dielectric layer on a sidewall of the second trench; and

filling a conducting material layer into the second trench, thereby forming a first gate electrode.

2. The fabricating method according to claim 1, wherein before or after the step of forming the second trench, the fabricating method further comprises a step of forming a first source/drain structure in the first zone.

3. The fabricating method according to claim 1, wherein the dielectric layer is formed by a chemical vapor deposition process, and the conducting material layer is made of poly-silicon.

4. The fabricating method according to claim 1, wherein after the step of filling the conducting material layer, the fabricating method further comprises steps of:

forming a flat layer to cover the conducting material layer;

performing a chemical mechanical polishing process to remove the flat layer and a portion of the conducting material layer; and

performing a blanket etching process to remove the conducting material layer and the dielectric layer overlying the first zone and the second zone.

5. The fabricating method according to claim 4, wherein after the conducting material layer and the dielectric layer overlying the first zone and the second zone are removed, the fabricating method further comprises steps of:

forming a second gate dielectric layer over the second zone;

forming a second gate electrode on the second gate dielectric layer; and

forming a second source/drain structure in the second zone.

6. The fabricating method according to claim 5, wherein before the step of forming the second source/drain structure, the fabricating method further comprises a step of covering a dielectric capping layer on the first gate electrode.

7. A fabricating method of a trench-gate metal oxide semiconductor device, the fabricating method comprising steps of:

defining a first zone and a second zone in a substrate;

forming a patterned hard mask layer over the first zone and the second zone;

performing an etching process to form at least one trench in the first zone by using the patterned hard mask layer as an etch mask;

forming a first gate dielectric layer on a sidewall of the trench;

filling a conducting material layer into the trench;

after filling the conducting material layer into the trench, applying a flattening process to the conducting material layer; and

performing a selective etching process to remove a portion of the conducting material layer filled in the trench, thereby forming a first gate electrode.

8. The fabricating method according to claim 7, wherein before the step of forming the patterned hard mask layer, the fabricating method further comprises steps of forming at least one isolation structure in the second zone.

9. The fabricating method according to claim 8, wherein the isolation structure is a shallow trench isolation layer and the conducting material layer is made of poly-silicon.

10. The fabricating method according to claim 8, wherein the patterned hard mask layer is a multi-layered structure including a silicon oxide thin film layer and a silicon nitride thick film layer, or the patterned hard mask layer is a multi-layered structure including a silicon oxide thick film layer and a silicon nitride thin film layer.

11. The fabricating method according to claim 7, wherein after the step of filling the conducting material layer and before the flattening process, the fabricating method further comprises steps of:

forming a flat layer to cover the conducting material layer;

wherein the chemical mechanical polishing process is performed to remove the flat layer, a portion of the conducting material layer and the patterned hard mask layer to expose a surface of the substrate, and the selective etching process is performed to make a top surface of the first gate electrode be lower than the surface of the substrate.

12. The fabricating method according to claim 11, wherein after the conducting material layer and the patterned hard mask layer overlying the first zone and the second zone are removed, the fabricating method further comprises steps of:

forming a second gate dielectric layer over the second zone;

forming a second gate electrode on the second gate dielectric layer; and

forming a second source/drain structure in the second zone.

13. The fabricating method according to claim 12, wherein before the step of forming the second source/drain structure, the fabricating method further comprises a step of covering a dielectric capping layer on the first gate electrode.