Methods of anneal after deposition of gate layers

• US 8,809,175 B2
• Filed: 07/15/2011
• Issued: 08/19/2014
• Est. Priority Date: 07/15/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chun Hsiung, Yu, Xiong-Fei, Huang, Yu-Lien, Lin, Da-Wen
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Newton, Valerie N
• Application Number:
  US13/183,909
• Publication Number:
  US 20130017678A1
• Time in Patent Office: 1,131 Days
• Field of Search: 438/926
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.

Claims

1. A method of fabricating a gate structure of a p-type metal-oxide-semiconductor transistor (PMOS) device on a silicon substrate, comprising:

forming the gate structure on the substrate, wherein the gate structure includes an opening after one or more dummy layers have been removed to form the opening;

forming an interfacial oxide layer on the silicon substrate in the opening;

depositing a high dielectric constant (high-k) dielectric layer over the interfacial oxide layer; and

performing a 2-stage preheat high-temperature anneal to reduce a number of interfacial sites at an interface between the silicon substrate and the interfacial oxide layer and to improve the PMOS negative bias temperature instability (NTBI) performance of the PMOS device, wherein a first stage preheat is performed at a temperature in a range from about 400°

C. to about 600°

C., and wherein a second stage preheat is performed at a temperature in a range from about 700°

C. to about 900°

C., and a high temperature anneal is performed at a peak temperature in a range from 875°

C. to about 1200°

C.

2. The method of claim 1, wherein a first duration of the first preheat is in a range from about 2 seconds to about 20 seconds and a second duration of the second preheat is in a range from about 1 second to about 20 seconds;

and wherein a third duration of the high temperature anneal is in a range from about 1 ms to about 5 seconds.

3. The method of claim 1, wherein the high-temperature anneal is a rapid thermal anneal (RTA) process, and wherein the second stage preheat is at a temperature in a range from about 750°

C. to about 800°

C. for a duration in a range from about 4 seconds to about 20 seconds, and wherein the high-temperature anneal is at a peak temperature in a range from about 875°

C. to about 1010°

C. for a T_peak-50C duration in a range from about 0.5 second to about 5 seconds.

4. The method of claim 1, wherein the high-temperature anneal is a millisecond anneal, and wherein the second stage preheat is at a temperature in a range from about 700°

C. to about 900C for a duration in a range from about 1 second to about 20 seconds, and wherein the high temperature anneal is at a peak temperature in a range from about 950°

C. to about 1200°

C. for a duration in a range from about 1 ms to about 40 ms.

5. The method of claim 1, further comprising:

depositing a conductive and metal-containing gate layer over the high-k dielectric layer.

6. The method of claim 5, wherein the conductive and metal-containing gate layer is selected from a group consisting of a first barrier layer, a p-type workfunction layer, or a second barrier layer.

7. The method of claim 5, wherein the 2-stage preheat high-temperature anneal is performed after the conductive and metal-containing gate layer is deposited.

8. The method of claim 1, wherein the 2-stage preheat high-temperature anneal is performed after the gate structure is fully formed.

9. The method of claim 5, wherein the p-type workfunction layer is selected from a group consisting of TiN, W, WN, or combinations thereof.

10. The method of claim 1, wherein the high-k dielectric layer contains HfO₂, HfSiO, HfSiON, HfTaO, HfSiO or HfZrO.

11. The method of claim 1, wherein the interfacial oxide layer is a native oxide formed after a wet clean, and wherein a thickness of the interfacial oxide layer is in a range from about 5 Å

to about 100 Å

.

12. The method of claim 1, wherein the 2-stage preheat high-temperature anneal is performed after the high dielectric constant (high-k) dielectric layer is deposited over the interfacial oxide layer.

13. The method of claim 1, wherein the 2-stage preheat improves the intermixing of the interfacial oxide layer and the high-k dielectric layer and the high-temperature anneal reduces the interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.

14. A method of fabricating a gate structure of a p-type metal-oxide-semiconductor transistor (PMOS) device on a silicon substrate, comprising:

forming the gate structure on the substrate, wherein the gate structure includes an opening after one or more dummy layers have been removed to form the opening;

forming an interfacial oxide layer on the silicon substrate in the opening;

depositing a high dielectric constant (high-k) dielectric layer over the interfacial oxide layer; and

performing a 2-stage preheat millisecond anneal to reduce a number of interfacial sites at an interface between the silicon substrate and the interfacial oxide layer and to improve the PMOS negative bias temperature instability (NTBI) performance of the PMOS device, wherein a first stage preheat is performed at a temperature in a range from about 400°

C. to about 600°

C. for a duration in a range from about 2 seconds to about 20 seconds, and wherein a second stage preheat is performed at a temperature in a range from about 700°

C. to about 900°

C. for a duration in a range from about 1 second to about 20 seconds, and a millisecond anneal is performed at a peak temperature in a range from 950°

C. to about 1200°

C. for a duration in a range from about 1 ms to about 40 ms.

15. The method of claim 14, further comprising:

depositing a conductive and metal-containing gate layer over the high-k dielectric layer, and wherein the metal gate layer is selected from a group consisting of a first barrier layer, a p-type workfunction layer, or a second barrier layer.

16. The method of claim 15, wherein the 2-stage preheat millisecond anneal is performed after the metal gate layer is deposited.

17. The method of claim 14, further comprising:

depositing a metal gate electrode layer, and wherein the 2-stage preheat millisecond anneal is performed after the metal gate electrode layer is deposited.

18. The method of claim 14, wherein the 2-stage preheat improves the intermixing of the interfacial oxide layer and the high-k dielectric layer and the high-temperature anneal reduces the interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.

19. A method of fabricating a gate structure of a p-type metal-oxide-semiconductor transistor (PMOS) device on a silicon substrate, comprising:

forming the gate structure on the substrate, wherein the gate structure includes an opening after one or more dummy layers have been removed to form the opening;

forming an interfacial oxide layer on the silicon substrate in the opening;

depositing a high dielectric constant (high-k) dielectric layer over the interfacial oxide layer; and

performing a 2-stage preheat spike anneal to reduce a number of interfacial sites at an interface between the silicon substrate and the interfacial oxide layer and to improve the PMOS negative bias temperature instability (NTBI) performance of the PMOS device, wherein a first stage preheat is performed at a temperature in a range from about 400°

C. to about 600°

C. for a duration in a range from about 2 seconds to about 20 seconds, and wherein a second stage preheat is performed at a temperature in a range from about 700°

C. to about 900°

C. for a duration in a range from about 1 second to about 20 seconds, and a spike anneal is performed at a peak temperature in a range from 875°

C. to about 1010°

C. for a duration in a range from about 0.5 second to about 5 seconds.

20. The method of claim 19, wherein the 2-stage preheat spike anneal is performed after the gate structure is fully formed.