Semiconductor device

• US 8,809,851 B2
• Filed: 05/05/2011
• Issued: 08/19/2014
• Est. Priority Date: 05/14/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kato, Kiyoshi, Shionoiri, Yutaka, Sekine, Yusuke, Furutani, Kazuma, Godo, Hiromichi
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/101,644
• Publication Number:
  US 20110278571A1
• Time in Patent Office: 1,202 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device including a first transistor and a second transistor and a capacitor which are over the first transistor is provided. A semiconductor layer of the second transistor includes an offset region. In the second transistor provided with an offset region, the off-state current of the second transistor can be reduced. Thus, a semiconductor device which can hold data for a long time can be provided.

Claims

1. A semiconductor device comprising:

a plurality of memory cells each comprising a first transistor, a second transistor, and a capacitor,

the first transistor comprising;

a first channel formation region;

a first insulating layer over the first channel formation region;

a first gate electrode over the first channel formation region with the first insulating layer interposed therebetween; and

a first electrode and a second electrode which are electrically connected to the first channel formation region,

the second transistor comprising;

an oxide semiconductor layer comprising a second channel formation region and an offset region in contact with the second channel formation region;

a third electrode and a fourth electrode which are electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the third electrode, and the fourth electrode; and

a second gate electrode over the second channel formation region with the second insulating layer interposed therebetween, and

wherein the first gate electrode, the third electrode, and one electrode of the capacitor are electrically connected to one another.

2. The semiconductor device according to claim 1, wherein the offset region is a region which overlaps with neither the second gate electrode, the third electrode, nor the fourth electrode.

3. The semiconductor device according to claim 1, wherein the first channel formation region comprises silicon.

4. The semiconductor device according to claim 1, further comprising a third gate electrode over the second insulating layer.

5. The semiconductor device according to claim 4, further comprising a fifth electrode between the second gate electrode and the third gate electrode, wherein the fifth electrode electrically connected to the oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises a first offset region and a second offset region,

wherein the first offset region is provided between the second gate electrode and the third electrode, and

wherein the second offset region is provided between the second gate electrode and the fourth electrode.

7. The semiconductor device according to claim 1, wherein the second gate electrode overlaps with neither the third electrode nor the fourth electrode.

8. The semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are in contact with an upper surface of the oxide semiconductor layer.

9. The semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are in contact with a lower surface of the oxide semiconductor layer.

10. The semiconductor device according to claim 1, wherein the first electrode and the fourth electrode are electrically connected to each other.

11. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region and an offset region adjacent to the channel formation region;

a first electrode and a second electrode which are electrically connected to the oxide semiconductor layer;

an insulating layer over the oxide semiconductor layer, the first electrode, and the second electrode;

a first gate electrode over the channel formation region with the insulating layer interposed therebetween; and

a third electrode over the first electrode with the insulating layer interposed therebetween,

wherein the first electrode and the second electrode overlap with the oxide semiconductor layer.

12. The semiconductor device according to claim 11, wherein the offset region is a region which overlaps with neither the first gate electrode, the first electrode, nor the second electrode.

13. The semiconductor device according to claim 11,

wherein the oxide semiconductor layer comprises a first offset region and a second offset region,

wherein the first offset region is provided between the first gate electrode and the first electrode, and

wherein the second offset region is provided between the first gate electrode and the second electrode.

14. The semiconductor device according to claim 11, wherein the first gate electrode overlaps with neither the first electrode nor the second electrode.

15. The semiconductor device according to claim 11, wherein the first electrode and the second electrode are in contact with an upper surface of the oxide semiconductor layer.

16. A semiconductor device comprising:

a first transistor comprising;

a first channel formation region;

a first insulating layer over the first channel formation region;

a first gate electrode over the first channel formation region with the first insulating layer interposed therebetween; and

a first electrode and a second electrode electrically connected to the first channel formation region,

a second transistor comprising;

an oxide semiconductor layer comprising a second channel formation region and an offset region adjacent to the second channel formation region;

a third electrode and a fourth electrode which are electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the third electrode, and the fourth electrode; and

a second gate electrode over the second channel formation region with the second insulating layer interposed therebetween,

wherein the first gate electrode and the third electrode are electrically connected to each other.

17. The semiconductor device according to claim 16, wherein the offset region is a region which overlaps with neither the second gate electrode, the third electrode, nor the fourth electrode.

18. The semiconductor device according to claim 16, wherein the first channel formation region comprises silicon.

19. The semiconductor device according to claim 16, further comprising a third gate electrode over the second insulating layer.

20. The semiconductor device according to claim 19, further comprising a fifth electrode between the second gate electrode and the third gate electrode, wherein the fifth electrode electrically connected to the oxide semiconductor layer.

21. The semiconductor device according to claim 16,

wherein the oxide semiconductor layer comprises a first offset region and a second offset region,

wherein the first offset region is provided between the second gate electrode and the third electrode, and

wherein the second offset region is provided between the second gate electrode and the fourth electrode.

22. The semiconductor device according to claim 16, wherein the second gate electrode overlaps with neither the third electrode nor the fourth electrode.

23. The semiconductor device according to claim 16, further comprising a fifth electrode over the third electrode with the second insulating layer interposed therebetween.

24. The semiconductor device according to claim 16, wherein the third electrode and the fourth electrode are in contact with an upper surface of the oxide semiconductor layer.

25. The semiconductor device according to claim 16, wherein the third electrode and the fourth electrode are in contact with a lower surface of the oxide semiconductor layer.

26. The semiconductor device according to claim 16, wherein the first electrode and the fourth electrode are electrically connected to each other.