Semiconductor device
First Claim
1. A semiconductor device comprising:
- a circuit comprising a first transistor; and
a memory element comprising a second transistor and a capacitor,wherein the second transistor comprises;
a first insulating layer;
a first trench in the first insulating layer;
a second trench in the first insulating layer;
an oxide semiconductor layer in contact with an inner wall surface of the first trench;
a second insulating layer adjacent to the oxide semiconductor layer, wherein the second insulating layer is adjacent to an inner wall surface of the second trench;
a gate electrode in the first trench and adjacent to the oxide semiconductor layer with the second insulating layer interposed therebetween;
a third insulating layer filling the second trench; and
a source electrode or a drain electrode in contact with the oxide semiconductor layer, andwherein the memory element is stacked over the circuit.
1 Assignment
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Accused Products
Abstract
A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced.
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Citations
27 Claims
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1. A semiconductor device comprising:
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a circuit comprising a first transistor; and a memory element comprising a second transistor and a capacitor, wherein the second transistor comprises; a first insulating layer; a first trench in the first insulating layer; a second trench in the first insulating layer; an oxide semiconductor layer in contact with an inner wall surface of the first trench; a second insulating layer adjacent to the oxide semiconductor layer, wherein the second insulating layer is adjacent to an inner wall surface of the second trench; a gate electrode in the first trench and adjacent to the oxide semiconductor layer with the second insulating layer interposed therebetween; a third insulating layer filling the second trench; and a source electrode or a drain electrode in contact with the oxide semiconductor layer, and wherein the memory element is stacked over the circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a semiconductor substrate provided with a first transistor; a second transistor over the first transistor, the second transistor comprising; a first insulating layer; a first trench in the first insulating layer; a first oxide semiconductor layer in contact with an inner wall surface of the first trench; a second insulating layer adjacent to the first oxide semiconductor layer; and a first gate electrode in the first trench and adjacent to the first oxide semiconductor layer with the second insulating layer interposed therebetween; and a third transistor over the second transistor, the third transistor comprising; a third insulating layer; a second trench in the third insulating layer; a second oxide semiconductor layer in contact with an inner wall surface of the second trench; a fourth insulating layer adjacent to the second oxide semiconductor layer; and a second gate electrode in the second trench and adjacent to the second oxide semiconductor layer with the fourth insulating layer interposed therebetween. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a semiconductor substrate provided with a first transistor; and a second transistor over the first transistor, the second transistor comprising; a first insulating layer; a first trench in the first insulating layer; a first oxide semiconductor layer in contact with the first insulating layer, wherein the first oxide semiconductor layer comprising; a first region adjacent to a first side wall of the first trench; a second region adjacent to a bottom surface of the first trench; and a third region adjacent to a second side wall of the first trench, the first side wall of the first trench being opposite to the second side wall of the first trench; a first source electrode on a first region of the first insulating layer, the first source electrode being in electrical contact with the first oxide semiconductor layer; a first drain electrode on a second region of the first insulating layer, the first drain electrode being in electrical contact with the first oxide semiconductor layer, wherein the first trench is located between the first region of the first insulating layer and the second region of the first insulating layer; a first gate insulating layer adjacent to the first oxide semiconductor layer; and a first gate electrode in the first trench and adjacent to the first oxide semiconductor layer with the first gate insulating layer interposed therebetween. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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Specification