Semiconductor device

• US 8,809,870 B2
• Filed: 01/20/2012
• Issued: 08/19/2014
• Est. Priority Date: 01/26/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Godo, Hiromichi
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US13/354,617
• Publication Number:
  US 20120187417A1
• Time in Patent Office: 942 Days
• Field of Search: 257/77
• US Class Current: 257/77
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced.

Claims

1. A semiconductor device comprising:

a circuit comprising a first transistor; and

a memory element comprising a second transistor and a capacitor,

wherein the second transistor comprises;

a first insulating layer;

a first trench in the first insulating layer;

a second trench in the first insulating layer;

an oxide semiconductor layer in contact with an inner wall surface of the first trench;

a second insulating layer adjacent to the oxide semiconductor layer, wherein the second insulating layer is adjacent to an inner wall surface of the second trench;

a gate electrode in the first trench and adjacent to the oxide semiconductor layer with the second insulating layer interposed therebetween;

a third insulating layer filling the second trench; and

a source electrode or a drain electrode in contact with the oxide semiconductor layer, and

wherein the memory element is stacked over the circuit.

2. The semiconductor device according to claim 1, wherein a gate electrode of the first transistor is electrically connected to one of a pair of electrodes included in the capacitor and the source electrode or the drain electrode in the second transistor.

3. The semiconductor device according to claim 1, wherein the second insulating layer is in contact with a side surface of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the first transistor comprises a semiconductor material other than an oxide semiconductor material, and

wherein the semiconductor material is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide.

6. The semiconductor device according to claim 1, further comprising a fourth insulating layer in the second trench,

wherein the fourth insulating layer is provided between the second insulating layer and the third insulating layer.

7. A semiconductor device comprising:

a semiconductor substrate provided with a first transistor;

a second transistor over the first transistor, the second transistor comprising;

a first insulating layer;

a first trench in the first insulating layer;

a first oxide semiconductor layer in contact with an inner wall surface of the first trench;

a second insulating layer adjacent to the first oxide semiconductor layer; and

a first gate electrode in the first trench and adjacent to the first oxide semiconductor layer with the second insulating layer interposed therebetween; and

a third transistor over the second transistor, the third transistor comprising;

a third insulating layer;

a second trench in the third insulating layer;

a second oxide semiconductor layer in contact with an inner wall surface of the second trench;

a fourth insulating layer adjacent to the second oxide semiconductor layer; and

a second gate electrode in the second trench and adjacent to the second oxide semiconductor layer with the fourth insulating layer interposed therebetween.

8. The semiconductor device according to claim 7,

wherein the second insulating layer is in contact with a side surface of the first oxide semiconductor layer, and

wherein the fourth insulating layer is in contact with a side surface of the second oxide semiconductor layer.

9. The semiconductor device according to claim 7,

wherein the first transistor and the second transistor are electrically connected to each other, and

wherein the second transistor and the third transistor are electrically connected to each other.

10. The semiconductor device according to claim 7, further comprising a first pair of electrodes in contact with the first oxide semiconductor layer,

wherein a gate electrode of the first transistor and one of the first pair of electrodes are electrically connected to each other.

11. The semiconductor device according to claim 10, further comprising a second pair of electrodes in contact with the second oxide semiconductor layer,

wherein the other of the first pair of electrodes and one of the second pair of electrodes are electrically connected to each other.

12. The semiconductor device according to claim 10, further comprising a first capacitor over the second transistor,

wherein the first capacitor is electrically connected to the first transistor and the second transistor.

13. The semiconductor device according to claim 10, further comprising a second capacitor over the third transistor,

wherein the second capacitor is electrically connected to the third transistor.

14. The semiconductor device according to claim 7, wherein the first oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to a surface of the first oxide semiconductor layer.

15. The semiconductor device according to claim 7, wherein the second oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to a surface of the second oxide semiconductor layer.

16. The semiconductor device according to claim 7,

wherein the first transistor comprises a semiconductor material, and

wherein the semiconductor material is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide.

17. The semiconductor device according to claim 7, further comprising a third trench in the first insulating layer,

wherein the second insulating layer is adjacent to an inner wall surface of the third trench, and

wherein a fifth insulating layer fills the third trench.

18. The semiconductor device according to claim 17, further comprising a fourth trench in the third insulating layer,

wherein the fourth insulating layer is adjacent to an inner wall surface of the fourth trench, and

wherein a sixth insulating layer fills the fourth trench.

19. A semiconductor device comprising:

a semiconductor substrate provided with a first transistor; and

a second transistor over the first transistor, the second transistor comprising;

a first insulating layer;

a first trench in the first insulating layer;

a first oxide semiconductor layer in contact with the first insulating layer, wherein the first oxide semiconductor layer comprising;

a first region adjacent to a first side wall of the first trench;

a second region adjacent to a bottom surface of the first trench; and

a third region adjacent to a second side wall of the first trench, the first side wall of the first trench being opposite to the second side wall of the first trench;

a first source electrode on a first region of the first insulating layer, the first source electrode being in electrical contact with the first oxide semiconductor layer;

a first drain electrode on a second region of the first insulating layer, the first drain electrode being in electrical contact with the first oxide semiconductor layer, wherein the first trench is located between the first region of the first insulating layer and the second region of the first insulating layer;

a first gate insulating layer adjacent to the first oxide semiconductor layer; and

a first gate electrode in the first trench and adjacent to the first oxide semiconductor layer with the first gate insulating layer interposed therebetween.

20. The semiconductor device according to claim 19, further comprising a third transistor over the second transistor, the third transistor comprising:

a second insulating layer;

a second trench in the second insulating layer;

a second oxide semiconductor layer in contact with the second insulating layer, wherein the second oxide semiconductor layer comprising;

a fourth region adjacent to a first side wall of the second trench;

a fifth region adjacent to a bottom surface of the second trench; and

a sixth region adjacent to a second side wall of the second trench, the first side wall of the second trench being opposite to the second side wall of the second trench;

a second source electrode on a first region of the second insulating layer, the second source electrode being in electrical contact with the second oxide semiconductor layer;

a second drain electrode on a second region of the second insulating layer, the second drain electrode being in electrical contact with the second oxide semiconductor layer, wherein the second trench is located between the first region of the second insulating layer and the second region of the second insulating layer;

a second gate insulating layer adjacent to the second oxide semiconductor layer; and

a second gate electrode in the second trench and adjacent to the second oxide semiconductor layer with the second gate insulating layer interposed therebetween.

21. The semiconductor device according to claim 19, wherein the first gate insulating layer is in contact with a side surface of the first oxide semiconductor layer.

22. The semiconductor device according to claim 19, wherein a gate electrode of the first transistor and the first source electrode are electrically connected to each other.

23. The semiconductor device according to claim 19, further comprising a capacitor over the second transistor,

wherein the capacitor is electrically connected to the first transistor and the second transistor.

24. The semiconductor device according to claim 19, wherein the first oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to a surface of the first oxide semiconductor layer.

25. The semiconductor device according to claim 19,

wherein the first transistor comprises a semiconductor material other than an oxide semiconductor material, and

wherein the semiconductor material is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide.

26. The semiconductor device according to claim 19, further comprising:

a third trench in the first insulating layer; and

a third insulating layer filling the third trench.

27. The semiconductor device according to claim 26, further comprising a fourth insulating layer in the third trench,

wherein the fourth insulating layer is provided between the first insulating layer and the third insulating layer.