Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks

• US 8,809,917 B2
• Filed: 07/29/2009
• Issued: 08/19/2014
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Huang, X. M. Henry, Rueckes, Thomas, Sivarajan, Ramesh
• Primary Examiner(s): GEBREMARIAM, SAMUEL A
• Application Number:
  US12/511,779
• Publication Number:
  US 20100072042A1
• Time in Patent Office: 1,847 Days
• Field of Search: 257/254, 257/415, 257/420
• US Class Current: 257/254
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10K 10/50 Bistable switching devices
• CPC Class Codes: H10K 85/221 : Carbon nanotubes
• CPC Class Codes: Y10S 977/943 : Information storage or retrieval using nanostructure

Abstract

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Claims

1. A nanotube memory device, comprising:

a first and second electrodes;

a switching element having a predetermined pattern comprising a porous network of non-woven nanotubes wherein at least a first nanotube is in electrical communication with the first electrode and at least a second nanotube is in electrical communication with the second electrode, wherein said porous network of non-woven nanotubes is capable of switching between at least two non-volatile resistive states; and

a protective barrier to protect the switching element.

2. The nanotube switch of claim 1, wherein the protective barrier includes a passivation layer that permeates at least partially into said porous network of nanotubes.

3. The nanotube memory device of claim 2 wherein said passivation layer is an insulator.

4. The nanotube memory device of claim 2, wherein said passivation layer is a conductor.

5. The nanotube memory device of claim 2, wherein said passivation layer is a semiconductor.

6. The nanotube memory device of claim 2, wherein said passivation layer is formed from at least one of SiO₂, SiN, Al₂O₃, and polyimide.

7. The nanotube memory device of claim 2, wherein said passivation layer is formed from at least one of phosphosilicate glass oxide, planarizing low temperature oxide, sputtered oxide, sputtered nitride, flowfill oxide, chemical vapor deposition of oxide and nitride, atomic layer deposition oxides, and polyvinylidene fluoride.

8. The nanotube memory device of claim 1, wherein the protective barrier seals the switching element.

9. The nanotube memory device of claim 1, wherein the protective barrier protects at least a portion of the switching element.

10. The nanotube memory device of claim 1, wherein the switching element is capable of switching between a plurality of electronic states in response to electrical stimuli applied to the first and second electrodes.