Semiconductor memory device

• US 8,809,927 B2
• Filed: 01/26/2012
• Issued: 08/19/2014
• Est. Priority Date: 02/02/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): JUNGE, BRYAN R.
• Application Number:
  US13/358,857
• Publication Number:
  US 20120193697A1
• Time in Patent Office: 936 Days
• Field of Search: 257/296, 257/301, 257/303, 257/306, 257328-330, 257/532, 438/156, 438/239, 438241-244, 438/253, 438/268, 438/270, 438/396, 365/51, 365/63, 365/185.05, 365/205, 365/207
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H10B 12/02 for one transistor one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F², or when a special structure is employed for a cell transistor, an area per memory cell less than or equal to 4F² can be achieved.

Claims

1. A semiconductor memory device comprising a memory cell array, the memory cell array comprising:

a first sense amplifier circuit and a second sense amplifier circuit;

first to fourth bit lines, an end of the first bit line and an end of the second bit line being electrically connected to the first sense amplifier circuit, and an end of the third bit line and an end of the fourth bit line being electrically connected to the second amplifier circuit;

an island-shaped semiconductor region over the first bit line;

a gate insulator over the island-shaped semiconductor region;

two word lines over the gate insulator and the island-shaped semiconductor region; and

a capacitor overlapping the island-shaped semiconductor region, over the two word lines,

wherein the third bit line is provided between the end of the first bit line and the end of the second bit line over the first sense amplifier circuit, and

wherein the second bit line is provided between the end of the third bit line and the end of the fourth bit line over the second sense amplifier circuit.

2. The semiconductor memory device according to claim 1, further comprising:

an electrode for connection with the first bit line, the electrode being provided between regions of the island-shaped semiconductor region over the two word lines.

3. The semiconductor memory device according to claim 1, further comprising a circuit for driving the memory cell array below the first bit line.

4. The semiconductor memory device according to claim 1, wherein the island-shaped semiconductor region includes a portion at a side surface of a recessed portion or a side surface of a projected portion.

5. The semiconductor memory device according to claim 1, wherein the first to fourth bit lines are formed in at least two different layers.

6. The semiconductor memory device according to claim 1, wherein the island-shaped semiconductor region includes an oxide semiconductor.

7. The semiconductor memory device according to claim 1, wherein the first bit line is connected to the island-shaped semiconductor region through a plug interposed between a top surface of the first bit line and a bottom surface of the island-shaped semiconductor region.

8. A semiconductor memory device comprising a memory cell array, the memory cell array comprising:

a first sense amplifier circuit and a second sense amplifier circuit;

first to fourth bit lines, an end of the first bit line and an end of the second bit line being electrically connected to the first sense amplifier circuit, and an end of the third bit line and an end of the fourth bit line being electrically connected to the second amplifier circuit;

an island-shaped semiconductor region over the first bit line;

a gate insulator over the island-shaped semiconductor region;

two word lines over the gate insulator and the island-shaped semiconductor region; and

a capacitor overlapping the island-shaped semiconductor region,

wherein the third bit line is provided between the end of the first bit line and the end of the second bit line over the first sense amplifier circuit,

wherein the second bit line is provided between the end of the third bit line and the end of the fourth bit line over the second sense amplifier circuit, and

wherein an area of the island-shaped semiconductor region that overlaps with the first bit line occupies 80% or more of an area of the island-shaped semiconductor region.

9. The semiconductor memory device according to claim 8, further comprising:

an electrode for connection with the first bit line, the electrode being provided between regions of the island-shaped semiconductor region over the two word lines.

10. The semiconductor memory device according to claim 8, further comprising a circuit for driving the memory cell array below the first bit line.

11. The semiconductor memory device according to claim 8, wherein the island-shaped semiconductor region includes a portion at a side surface of a recessed portion or a side surface of a projected portion.

12. The semiconductor memory device according to claim 8, wherein the first to fourth bit lines are formed in at least two different layers.

13. The semiconductor memory device according to claim 8, wherein the island-shaped semiconductor region includes an oxide semiconductor.

14. The semiconductor memory device according to claim 8, wherein the first bit line is connected to the island-shaped semiconductor region through a plug interposed between a top surface of the first bit line and a bottom surface of the island-shaped semiconductor region.

15. A semiconductor memory device comprising a memory cell array, the memory cell array comprising:

a first sense amplifier circuit and a second amplifier circuit;

first to fourth bit lines, an end of the first bit line and an end of the second bit line being electrically connected to the first sense amplifier circuit, and an end of the third bit line and an end of the fourth bit line being electrically connected to the second amplifier circuit;

an island-shaped semiconductor region over the first bit line;

a gate insulator over the island-shaped semiconductor region;

two word lines over the gate insulator and the island-shaped semiconductor region; and

a capacitor over the island-shaped semiconductor region,

wherein the third bit line is provided between the end of the first bit line and the end of the second bit line over the first sense amplifier circuit,

wherein the second bit line is provided between the end of the third bit line and the end of the fourth bit line over the second sense amplifier circuit, and

wherein the bit lines do not cross over one another.

16. The semiconductor memory device according to claim 15, further comprising an electrode for connection with the first bit line, the electrode being provided between regions of the island-shaped semiconductor region over the two word lines.

17. The semiconductor memory device according to claim 15, further comprising a circuit for driving the memory cell array below the first bit lines.

18. The semiconductor memory device according to claim 15, wherein the island-shaped semiconductor region includes a portion at a side surface of a recessed portion or a side surface of a projected portion.

19. The semiconductor memory device according to claim 15, wherein the first to fourth bit lines are formed in at least two different layers.

20. The semiconductor memory device according to claim 15, wherein the island-shaped semiconductor region includes an oxide semiconductor.