Chip packages having dual DMOS devices with power management integrated circuits

• US 8,809,951 B2
• Filed: 09/23/2013
• Issued: 08/19/2014
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megit Acquisition Corp.
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US14/034,440
• Publication Number:
  US 20140021522A1
• Time in Patent Office: 330 Days
• Field of Search: 257/335, 257/531, 257/532, 257/724, 257/E25.029
• US Class Current: 257/335
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0615 : Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16245 : the item being metallic
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.

Claims

1. A semiconductor chip comprising:

a semiconductor substrate;

a first double-diffused metal oxide semiconductor (DMOS) device on the semiconductor substrate;

a second DMOS device on the semiconductor substrate;

a capacitor coupled to the semiconductor substrate; and

an inductor coupled to the semiconductor substrate, the inductor including a first terminal coupled to the first and second DMOS devices, and a second terminal coupled to the capacitor.

2. The semiconductor chip of claim 1 further comprising a passivation layer coupled to the semiconductor substrate and the capacitor, the passivation layer comprising a nitride layer.

3. The semiconductor chip of claim 2, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

4. The semiconductor chip of claim 1 further comprising a passivation layer coupled to the semiconductor substrate and the inductor, the passivation layer comprising a nitride layer.

5. The semiconductor chip of claim 4, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

6. The semiconductor chip of claim 1 further comprising a polymer layer coupled to the inductor.

7. The semiconductor chip of claim 6 further comprising a tin-containing joint at a bottom of the capacitor.

8. The semiconductor chip of claim 1, wherein the inductor comprises a copper layer having a thickness between 1.5 and 15 micrometers.

9. A semiconductor chip comprising:

a semiconductor substrate;

a first double-diffused metal oxide semiconductor (DMOS) device on the semiconductor substrate;

a second DMOS device on the semiconductor substrate;

a first capacitor coupled to the semiconductor substrate;

an inductor coupled to the semiconductor substrate, wherein the inductor includes a first terminal coupled to a first terminal of the first DMOS device and to a first terminal of the second DMOS device, and a second terminal of the inductor is coupled to the first capacitor;

a switch controller coupled to a gate of the first DMOS device and to a gate of the second DMOS device; and

a voltage feedback device having a first terminal coupled to the second terminal of the inductor and to the first capacitor and a second terminal coupled to the switch controller.

10. The semiconductor chip of claim 9 further comprising a passivation layer coupled to the semiconductor substrate and the first capacitor, the passivation layer comprising a nitride layer.

11. The semiconductor chip of claim 10, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

12. The semiconductor chip of claim 9 further comprising a passivation layer coupled to the semiconductor substrate and the inductor, the passivation layer comprising a nitride layer.

13. The semiconductor chip of claim 12, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

14. The semiconductor chip of claim 9 further comprising a second capacitor coupled to a second terminal of the first DMOS device.

15. The semiconductor chip of claim 14 further comprising a passivation layer coupled to the semiconductor substrate and the second capacitor, the passivation layer comprising a nitride layer.

16. The semiconductor chip of claim 15, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

17. A semiconductor chip comprising:

a semiconductor substrate;

an inductor coupled to the semiconductor substrate;

a first capacitor coupled to the semiconductor substrate;

a first double-diffused metal oxide semiconductor (DMOS) device on the semiconductor substrate, the first DMOS device being coupled to a first terminal of the inductor;

a second DMOS device on the semiconductor substrate, the second DMOS device including;

a gate coupled to the first terminal of the inductor and to the first DMOS device,

a first terminal coupled to the first terminal of the inductor, the first DMOS device and to the gate of the second DMOS device, and

a second terminal coupled to the first capacitor;

a switch controller coupled to a gate of the first DMOS device; and

a voltage feedback device having;

a first terminal coupled to the second terminal of the second DMOS device and to the first capacitor, and

a second terminal coupled to the switch controller.

18. The semiconductor chip of claim 17 further comprising a passivation layer coupled to the semiconductor substrate and the first capacitor, the passivation layer comprising a nitride layer.

19. The semiconductor chip of claim 18, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

20. The semiconductor chip of claim 17 further comprising a passivation layer coupled to the semiconductor substrate and the inductor, the passivation layer comprising a nitride layer.

21. The semiconductor chip of claim 20, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.

22. The semiconductor chip of claim 17 further comprising a second capacitor coupled to a second terminal of the inductor.

23. The semiconductor chip of claim 22 further comprising a passivation layer coupled to the semiconductor substrate and the second capacitor, the passivation layer comprising a nitride layer.

24. The semiconductor chip of claim 23, wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.