Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

• US 8,810,024 B2
• Filed: 03/23/2012
• Issued: 08/19/2014
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Lin, Yaojian, Marimuthu, Pandi Chelvam, Chen, Kang, Gu, Yu
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/429,119
• Publication Number:
  US 20130249115A1
• Time in Patent Office: 879 Days
• Field of Search: 438/666, 438/667, 438/125, 257/618, 257/621, 257/687
• US Class Current: 257/698
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24155 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a carrier with a die attach area;

disposing a semiconductor die over the die attach area;

disposing a modular interconnect unit over the carrier in a peripheral region around the semiconductor die;

depositing an encapsulant over the carrier, semiconductor die, and modular interconnect unit;

removing a first portion of the encapsulant to expose the semiconductor die while leaving a second portion of the encapsulant over the modular interconnect unit;

removing the carrier; and

forming an interconnect structure over the semiconductor die or modular interconnect unit.

2. The method of claim 1, wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core and overlapping the core by 0-200 micrometers.

3. The method of claim 2, wherein the vertical interconnect structure includes an opening filled with a conductive paste or a polymer plug.

4. The method of claim 1, wherein the modular interconnect unit is offset from the semiconductor die.

5. The method of claim 1, wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

6. The method of claim 1, further including removing the second portion of the encapsulant to expose the modular interconnect unit.

7. A method of making a semiconductor device, comprising:

providing a plurality of individual modular interconnect units;

disposing a first individual modular interconnect unit of the plurality of individual modular interconnect units offset from a semiconductor die in a peripheral region around the semiconductor die;

depositing an encapsulant over the semiconductor die and first individual modular interconnect unit; and

removing the encapsulant to expose the semiconductor die.

8. The method of claim 7, wherein the first individual modular interconnect unit includes a core with a vertical interconnect structure formed through the core.

9. The method of claim 7, wherein the first individual modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

10. The method of claim 7, further including forming an insulating layer over a back surface of the semiconductor die prior to exposing the first individual modular interconnect unit with respect to the encapsulant.

11. The method of claim 7, wherein removing the encapsulant further includes:

removing a first portion of the encapsulant from over the semiconductor die to expose a back surface of the semiconductor die while leaving a second portion of the encapsulant over the first individual modular interconnect unit; and

removing the second portion of the encapsulant to expose the first individual modular interconnect unit.

12. The method of claim 7, wherein the first individual modular interconnect unit forms a part of an interlocking pattern around the semiconductor die.

13. The method of claim 7, further including forming an insulating layer over the semiconductor device to reduce warpage.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing a modular interconnect unit in a peripheral region around the semiconductor die and offset from the semiconductor die; and

depositing an encapsulant over the semiconductor die and modular interconnect unit.

15. The method of claim 14, wherein the modular interconnect unit includes a core with a conductive interconnect structure formed through the core.

16. The method of claim 15, wherein the conductive interconnect structure includes a metal cap and a protective layer formed over the metal cap.

17. The method of claim 15, wherein the modular interconnect unit includes multiple rows of vertical interconnect structures or bumps.

18. The method of claim 14, wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

19. The method of claim 14, further including forming an insulating layer over a back surface of the semiconductor die prior to exposing the modular interconnect unit with respect to the encapsulant.

20. The method of claim 14, further including forming an insulating layer over the semiconductor device to reduce warpage.

21. A semiconductor device, comprising:

a semiconductor die;

a modular interconnect unit disposed in a peripheral region around the semiconductor die with a height of the modular interconnect unit less than a height of the semiconductor die; and

an encapsulant deposited around the semiconductor die and modular interconnect unit.

22. The semiconductor device of claim 21, wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core.

23. The semiconductor device of claim 21, wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

24. The semiconductor device of claim 21, wherein the modular interconnect unit forms a part of an interlocking pattern around the semiconductor die.

25. The semiconductor device of claim 21, further including an insulating layer formed over the semiconductor device to reduce warpage.

26. The semiconductor device of claim 22, wherein the vertical interconnect structure includes a conductive material and a filler material.

27. A method of making a semiconductor device, comprising:

providing a modular interconnect unit including a vertical interconnect structure; and

disposing a semiconductor die around the modular interconnect unit.

28. The method of claim 27, wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

29. The method of claim 27, wherein the vertical interconnect structure includes a first conductive material and a filler material.

30. The method of claim 29, wherein the filler material is an insulating material.

31. The method of claim 29, wherein the filler material is a second conductive material.

32. The method of claim 29, wherein the filler material is void.