Method and system for controlling HS-NMOS power switches with slew-rate limitation

• US 8,810,303 B2
• Filed: 10/18/2013
• Issued: 08/19/2014
• Est. Priority Date: 09/07/2010
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Brauer, Michael, Drebinger, Stephan
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US14/057,046
• Publication Number:
  US 20140043077A1
• Time in Patent Office: 305 Days
• Field of Search: 327365-508
• US Class Current: 327/376
• CPC Class Codes: H03K 17/166 Soft switching
• CPC Class Codes: H03K 2017/6875 using self-conductive, depletion FETs
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125

Abstract

A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Claims

1. A method for controlling an array of power switches with slew-rate limit, comprising the following steps:

(1) providing an array of HS-NMOS power switches comprising a multitude of switch driver cells each controlling a correspondent power switch, and a charge pump;

(2) limiting slew rate of the power switch;

(3) deploying only one charge pump for the total array of power switches, wherein the charge pump is isolated from the multitude of switch drivers; and

(4) establishing zero current draw from the charge pump in case of a steady state of a power switch;

wherein said zero current in steady state is established by steps of;

sampling a gate voltage of the power switch when power switch is enabled;

turning gate of power switch fully ON;

then

reducing all currents drawn from the charge pump for the correspondent driver cell to zero; and

latch the state of previous step until a control signal goes low and then high again.

2. The method of claim 1, wherein the slew rate of the power switch is limited by driving a power switch such that its output voltage waveform follows a linear ramp.

3. The method of claim 2, wherein the output voltage waveform follows a linear ramp by adding a capacitive feedback sampling an instantaneous output voltage.

4. The method of claim 1, wherein the charge pump is isolated by adding one current source per switch driver.

5. The method of claim 1, wherein a pre-biasing scheme for a current mirror controlling the power switch is used to eliminate an undesired situation of an open regulation loop which could occur when an output voltage of the power switch is lower than a threshold voltage of a transistor of this current mirror.

6. The method of claim 1, wherein an effective threshold voltage of a current mirror controlling the power switch is reduced in order to minimize a side effect of no slew-rate limiting in case of low output voltages.