Semiconductor memory device including multilayer wiring layer

• US 8,811,064 B2
• Filed: 01/06/2012
• Issued: 08/19/2014
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Takemura, Yasuhiko
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/344,921
• Publication Number:
  US 20120182790A1
• Time in Patent Office: 956 Days
• Field of Search: 257/296, 257/758, 365/149
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 5/10 for interconnecting capacitors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

Claims

1. A semiconductor memory device comprising:

a driver circuit comprising part of a single crystal semiconductor substrate;

a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and

a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,

wherein the memory cell is electrically connected to the driver circuit through the wiring,

wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,

wherein the wiring includes copper or a copper alloy, and

wherein a channel region of the transistor is included in an oxide semiconductor layer.

2. The semiconductor memory device according to claim 1, wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.

3. The semiconductor memory device according to claim 1, wherein the capacitor is a stack capacitor.

4. The semiconductor memory device according to claim 1, wherein the single crystal semiconductor substrate is a single crystal silicon substrate.

15. The semiconductor memory device according to claim 1, wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.

5. A semiconductor memory device comprising:

a driver circuit comprising part of a single crystal semiconductor substrate;

a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and

a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,

wherein the memory cell is electrically connected to the driver circuit through the wiring,

wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,

wherein the wiring includes copper or a copper alloy,

wherein a channel region of the transistor is included in an oxide semiconductor layer, and

wherein the capacitor overlaps the transistor.

6. The semiconductor memory device according to claim 5, wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.

7. The semiconductor memory device according to claim 5, wherein the capacitor is a stack capacitor.

8. The semiconductor memory device according to claim 5, wherein the single crystal semiconductor substrate is a single crystal silicon substrate.

16. The semiconductor memory device according to claim 5, wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.

9. A semiconductor memory device comprising:

a driver circuit;

a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and

a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,

wherein the memory cell is electrically connected to the driver circuit through the wiring,

wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,

wherein the wiring includes copper or a copper alloy, and

wherein a channel region of the transistor is included in an oxide semiconductor layer.

10. The semiconductor memory device according to claim 9, wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.

11. The semiconductor memory device according to claim 9, wherein the capacitor is a stack capacitor.

17. The semiconductor memory device according to claim 9, wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.

12. A semiconductor memory device comprising:

a driver circuit;

a multilayer wiring layer overlapping the driver circuit, and the multilayer wiring layer comprising a wiring; and

a memory cell array layer overlapping the multilayer wiring layer, and the memory cell array layer comprising a memory cell,

wherein the memory cell is electrically connected to the driver circuit through the wiring,

wherein the memory cell comprises a transistor and a capacitor, and an electrode of the capacitor is electrically connected to one of a source and a drain of the transistor,

wherein the wiring includes copper or a copper alloy,

wherein a channel region of the transistor is included in an oxide semiconductor layer, and

wherein the capacitor overlaps the transistor.

13. The semiconductor memory device according to claim 12, wherein the other of the source and the drain of the transistor is electrically connected to the driver circuit through the wiring.

14. The semiconductor memory device according to claim 12, wherein the capacitor is a stack capacitor.

18. The semiconductor memory device according to claim 12, wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.