Performing error detection on DRAMs

• US 8,811,065 B2
• Filed: 09/14/2012
• Issued: 08/19/2014
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Smith, Michael John Sebastian, Wang, David T.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/620,565
• Publication Number:
  US 20130100746A1
• Time in Patent Office: 704 Days
• Field of Search: 365/149, 365/150, 365/233.1
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.

Claims

1. A memory module comprising:

a plurality of groups of dynamic random access memory (DRAM) integrated circuits comprising a first group, each group of DRAM integrated circuits including a plurality of data-storing DRAM integrated circuits and a tag-storing DRAM integrated circuit that is distinct from the plurality of data-storing DRAM integrated circuits, wherein the plurality of data-storing DRAM integrated circuits of the first group store first data, and wherein the tag-storing DRAM integrated circuit of the first group stores error-checking information associated with the first data; and

an interface circuit for providing an interface between the plurality of groups of DRAM integrated circuits and a memory controller, the interface circuit configured to;

receive a read command from the memory controller for the first data;

read the first data from the plurality of data-storing DRAM integrated circuits of the first group;

determine that the first data as read is erroneous; and

recover the first data using at least the error-checking information from the tag-storing DRAM integrated circuit of the first group, in response to determining that the first data as read is erroneous.

2. The memory module of claim 1, wherein the interface circuit is further configured to:

provide the first data to the memory controller;

receive a signal from the memory controller indicating that the first data provided to the memory controller is erroneous;

determine that the first data as read is erroneous based on the received signal; and

provide the recovered first data to the memory controller.

3. The memory module of claim 1, wherein the interface circuit is further configured to:

generate error-checking data using the first data as read;

determine that the error-checking data does not match the error-checking information; and

determine that the first data as read is erroneous before providing the first data to the memory controller, in response to determining that the error-checking data does not match the error-checking information.

4. The memory module of claim 1, wherein the error-checking information associated with the first data is generated using a Redundant Array of Inexpensive Disks (RAID) technique.

5. The memory module of claim 4, wherein the interface circuit is further configured to:

split the first data into a number of data blocks corresponding to a count of the data-storing DRAM integrated circuits of the first group;

store the data blocks in respective DRAM integrated circuits of the data-storing DRAM integrated circuits of the first group; and

determine the error-checking information based on the data blocks.

6. The memory module of claim 5, wherein the error-checking information is a value generated using XOR operations of the data blocks.

7. The memory module of claim 1, wherein the interface circuit is further configured to:

identify which particular data-storing DRAM integrated circuit of the plurality of data-storing DRAM integrated circuits caused the first data as read to be erroneous based on the error-checking information.

8. The memory module of claim 7, wherein the interface circuit is further configured to:

store a corresponding portion of the recovered first data in the particular data-storing DRAM integrated circuit.

9. The memory module of claim 7, wherein the interface circuit is further configured to:

determine that a count of errors caused by the particular data-storing DRAM integrated circuit is greater than a threshold; and

determine that the particular data-storing DRAM integrated circuit is a failed DRAM integrated circuit, in response to determining that the count of errors is greater than the threshold.

10. The memory module of claim 9, wherein the plurality of DRAM integrated circuits include one or more redundancy DRAM integrated circuits.

11. The memory module of claim 10, wherein the interface circuit is further configured to:

store the corresponding portion of the recovered first data in the particular redundancy DRAM integrated circuit, in response to determining that the particular data-storing DRAM integrated circuit is a failed DRAM integrated circuit.

12. The memory module of claim 1, wherein the plurality of DRAM integrated circuits of the first group and the interface circuit are stacked.

13. The memory module of claim 1, wherein each of the plurality of DRAM integrated circuits of the plurality of groups is a packaged DRAM integrated circuit.

14. The memory module of claim 1, wherein each of the plurality of DRAM integrated circuits of the plurality of groups is a DRAM integrated circuit die.

15. An apparatus comprising:

a memory controller;

a plurality of groups of DRAM integrated circuits comprising a first group, each group of DRAM integrated circuits including a plurality of data-storing DRAM integrated circuits and a tag-storing DRAM integrated circuit that is distinct from the plurality of data-storing DRAM integrated circuits, wherein the plurality of data-storing DRAM integrated circuits of the first group store first data, and wherein the tag-storing DRAM integrated circuit of the first group stores error-checking information associated with the first data; and

an interface circuit for providing an interface between the plurality of groups of DRAM integrated circuits and the memory controller, the interface circuit configured to;

receive a read command from the memory controller for the first data;

read the first data from the plurality of data-storing DRAM integrated circuits of the first group;

determine that the first data as read is erroneous; and

recover the first data using at least the error-checking information from the tag-storing DRAM integrated circuit of the first group, in response to determining that the first data as read is erroneous.

16. The apparatus of claim 15, wherein the interface circuit is further configured to:

provide the first data to the memory controller;

receive a signal from the memory controller indicating that the first data provided to the memory controller is erroneous;

determine that the first data as read is erroneous based on the received signal; and

provide the recovered first data to the memory controller.

17. The apparatus of claim 15, wherein the interface circuit is further configured to:

generate error-checking data using the first data as read;

determine that the error-checking data does not match the error-checking information; and

determine that the first data as read is erroneous before providing the first data to the memory controller, in response to determining that the error-checking data does not match the error-checking information.

18. The apparatus of claim 15, wherein the error-checking information associated with the first data is generated using a Redundant Array of Inexpensive Disks (RAID) technique.

19. The apparatus of claim 18, wherein the interface circuit is further configured to:

split the first data into a number of data blocks corresponding to a count of the data-storing DRAM integrated circuits of the first group;

store the data blocks in respective DRAM integrated circuits of the data-storing DRAM integrated circuits of the first group; and

determine the error-checking information based on the data blocks.

20. A memory module comprising:

a plurality of groups of DRAM integrated circuits, each group of DRAM integrated circuits including a plurality of data-storing DRAM integrated circuits and a tag-storing DRAM integrated circuit that is distinct from the plurality of data-storing DRAM integrated circuits, wherein the plurality of data-storing DRAM integrated circuits of each group store respective data, and wherein the tag-storing DRAM integrated circuit of each group stores respective error-checking information associated with the respective data; and

a plurality of interface circuits, each interface circuit providing an interface between a memory controller and a respective corresponding group of DRAM integrated circuits, each interface circuit configured to;

provide an interface between the memory controller and the respective corresponding group;

receive a read command from the memory controller for data stored in the respective corresponding group;

read the data from the plurality of data-storing DRAM integrated circuits of the respective corresponding group;

determine that the data as read is erroneous; and

recover the data using at least the error-checking information from the tag-storing DRAM integrated circuit of the respective corresponding group, in response to determining that the first data is erroneous.