Semiconductor memory device and driving method thereof

• US 8,811,066 B2
• Filed: 03/08/2013
• Issued: 08/19/2014
• Est. Priority Date: 01/22/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Takemura, Yasuhiko
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/790,044
• Publication Number:
  US 20130194858A1
• Time in Patent Office: 529 Days
• Field of Search: 365/149, 365/63, 365/72, 365/102, 365/154
• US Class Current: 365/149
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.

Claims

1. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising;

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor,

wherein a gate of the first transistor is electrically connected to the first line,

wherein one of a source and a drain of the second transistor is electrically connected to the third line,

wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line,

wherein the other of electrodes of the capacitor is electrically connected to the second line,

wherein the first transistor comprises a semiconductor layer including an oxide semiconductor,

wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor,

wherein the semiconductor device is configured to write a plurality of stages of data to the memory cell,

wherein the semiconductor device is configured to read the plurality of stages of data from the memory cell, and

wherein the plurality of stages of data is larger than or equal to three stages of data.

2. The semiconductor device according to claim 1, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a channel width of the first transistor.

3. The semiconductor device according to claim 1, wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

4. The semiconductor device according to claim 1, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

5. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising;

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor,

wherein a gate of the first transistor is electrically connected to the first line,

wherein one of a source and a drain of the second transistor is electrically connected to the third line,

wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line,

wherein the other of electrodes of the capacitor is electrically connected to the second line,

wherein the first transistor comprises a semiconductor layer including an oxide semiconductor,

wherein the semiconductor device is configured to write a plurality of stages of data to the memory cell,

wherein the semiconductor device is configured to read the plurality of stages of data from the memory cell,

wherein the plurality of stages of data is larger than or equal to three stages of data, and

wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

6. The semiconductor device according to claim 5, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.

7. A semiconductor device comprising:

a first line;

a second line;

a third line;

a fourth line; and

a memory cell comprising;

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor,

wherein a gate of the first transistor is electrically connected to the first line,

wherein one of a source and a drain of the second transistor is electrically connected to the third line,

wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line,

wherein the other of electrodes of the capacitor is electrically connected to the second line,

wherein the first transistor comprises a semiconductor layer including an oxide semiconductor,

wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor,

wherein the semiconductor device is configured to write a plurality of stages of data to the memory cell,

wherein the semiconductor device is configured to read the plurality of stages of data from the memory cell,

wherein the plurality of stages of data is larger than or equal to three stages of data,

wherein the semiconductor layer includes a first impurity region and a second impurity region, and

wherein the first impurity region and the second impurity region are formed in a self-aligned manner with respect to the gate of the first transistor.

8. The semiconductor device according to claim 7, wherein a width of the second line is greater than or equal to 0.5 times and less than or equal to 1.5 times a channel width of the first transistor.

9. The semiconductor device according to claim 7, wherein leakage current between the source and the drain of the first transistor in an off state is 1×

10<sup>−

20</sup> A or smaller at a temperature of 25°

C.

10. The semiconductor device according to claim 7, wherein carrier concentration of the oxide semiconductor is less than 1×

10¹⁴ cm<sup>−

3</sup>.