Semiconductor device

• US 8,811,067 B2
• Filed: 02/19/2014
• Issued: 08/19/2014
• Est. Priority Date: 11/06/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/183,644
• Publication Number:
  US 20140169072A1
• Time in Patent Office: 181 Days
• Field of Search: 365/149, 365/185.23, 365/189.09, 365/63, 365/189.07
• US Class Current: 365/149
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Claims

1. A method for driving a semiconductor device comprising:

a first line;

a second line;

a memory cell;

a first circuit electrically connected to the first line; and

a second circuit electrically connected to the second line,

the method comprising a writing step and a reading step, the writing step comprising steps of;

selecting one of a plurality of writing potentials; and

outputting the one of the plurality of wiring potentials to the first line, and the reading step comprising a step of;

comparing a potential of the second line and a plurality of reference potentials, wherein the memory cell comprises;

a first transistor including a first gate, a first source and a first drain;

a second transistor including a second gate, a second source and a second drain; and

a third transistor including a third gate, a third source and a third drain,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate and one of the second source and the second drain are electrically connected to each other,

wherein the first drain and the third source are electrically connected to each other,

wherein the second line and the third drain are electrically connected to each other, and

wherein the first line and the other of the second source and the second drain are electrically connected to each other.

2. The method according to claim 1, wherein the memory cell further comprises a capacitor electrically connected to the first gate.

3. The method according to claim 1, the semiconductor device further comprises a third circuit,

the method further comprising:

generating and supplying the plurality of writing potentials to the first circuit; and

generating and supplying the plurality of reference potentials to the second circuit.

4. The method according to claim 1, wherein the oxide semiconductor layer includes In, Ga and Zn.

5. The method according to claim 1, wherein the oxide semiconductor layer includes a crystal of In₂Ga₂ZnO₇.

6. The method according to claim 1, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

7. The method according to claim 1, wherein off current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

8. A method for driving a semiconductor device comprising:

a first line;

a second line;

a memory cell;

a first circuit electrically connected to the first line; and

a second circuit electrically connected to the second line,

the method comprising a writing step and a reading step, the writing step comprising steps of;

selecting one of a plurality of writing potentials; and

outputting the one of the plurality of wiring potentials to the first line, and the reading step comprising a step of;

comparing a potential of the second line and a plurality of reference potentials, wherein the memory cell comprises;

a first transistor including a first gate, a first source and a first drain;

a second transistor including a second gate, a second source and a second drain; and

a capacitor,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate and one of the second source and the second drain are electrically connected to each other,

wherein the first gate and one electrode of the capacitor are electrically connected to each other,

wherein the second line and the first drain are electrically connected to each other, and

wherein the first line and the other of the second source and the second drain are electrically connected to each other.

9. The method according to claim 8, wherein the memory cell further comprises a third circuit,

the method further comprising:

generating and supplying the plurality of writing potentials to the first circuit; and

generating and supplying the plurality of reference potentials to the second circuit.

10. The method according to claim 8, wherein the oxide semiconductor layer includes In, Ga and Zn.

11. The method according to claim 8, wherein the oxide semiconductor layer includes a crystal of In₂Ga₂ZnO₇.

12. The method according to claim 8, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

13. The method according to claim 8, wherein off current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

14. A method for driving a semiconductor device comprising:

a first line;

a second line;

a third line;

a plurality of memory cells electrically connected to each other in parallel between the second line and the third line;

a first circuit electrically connected to the first line; and

a second circuit electrically connected to the second line,

the method comprising a writing step and a reading step, the writing step comprising steps of;

selecting one of a plurality of writing potentials; and

outputting the one of the plurality of wiring potentials to the first line, and the reading step comprising a step of;

comparing a potential of the second line and a plurality of reference potentials,

wherein one of the plurality of memory cells comprises;

a first transistor including a first gate, a first source and a first drain;

a second transistor including a second gate, a second source and a second drain; and

a capacitor,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate and one of the second source and the second drain are electrically connected to each other,

wherein the first gate and one electrode of the capacitor are electrically connected to each other,

wherein the second line and the first drain are electrically connected to each other, and

wherein the first line and the other of the second source and the second drain are electrically connected to each other.

15. The method according to claim 14, wherein the one of the plurality of memory cells further comprises a third circuit,

the method further comprising:

generating and supplying the plurality of writing potentials to the first circuit; and

generating and supplying the plurality of reference potentials to the second circuit.

16. The method according to claim 14, wherein the oxide semiconductor layer includes In, Ga and Zn.

17. The method according to claim 14, wherein the oxide semiconductor layer includes a crystal of In₂Ga₂ZnO₇.

18. The method according to claim 14, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

19. The method according to claim 14, wherein off current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.