Integrated circuit devices and methods
First Claim
Patent Images
1. An integrated circuit comprising:
- multiple SRAM cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; and
the pull-up transistors, the pull-down transistors, and the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer,wherein the screening region provides an enhanced body coefficient for the pull-up transistors, the enhanced body coefficient acting to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region.
2 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer. The screening region has a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer. The screening region can provide an enhanced body coefficient for the pull-up transistors to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. Related methods are also disclosed.
-
Citations
33 Claims
-
1. An integrated circuit comprising:
-
multiple SRAM cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; and the pull-up transistors, the pull-down transistors, and the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, wherein the screening region provides an enhanced body coefficient for the pull-up transistors, the enhanced body coefficient acting to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
-
-
29. An integrated circuit comprising:
-
multiple SRAM cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors; the pull-up transistors, the pull-down transistors, and the pass-gate transistors having a screening region that is formed across multiple transistors before the creation of transistor isolation structures, the screening region having a substantially uniform concentration of screening region dopants in a lateral plane, the screening regions to provide reduced threshold voltage variations for the pull-up transistors, the pull-down transistors, and the pass-gate transistors in the SRAM cells, the reduced threshold voltage variations to increase the read static noise margin of the SRAM cell. - View Dependent Claims (30, 31, 32)
-
-
33. A method for operating an integrated circuit comprising:
-
employing multiple SRAM cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; and forming a screening region, the pull-up transistors, the pull-down transistors, and the pass-gate transistors having the screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer; and applying a body bias voltage to the screening region, wherein the screening region provides an enhanced body coefficient for the pull-up transistors, the enhanced body coefficient acting to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region.
-
Specification