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Integrated circuit devices and methods

  • US 8,811,068 B1
  • Filed: 05/14/2012
  • Issued: 08/19/2014
  • Est. Priority Date: 05/13/2011
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • multiple SRAM cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; and

    the pull-up transistors, the pull-down transistors, and the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer,wherein the screening region provides an enhanced body coefficient for the pull-up transistors, the enhanced body coefficient acting to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region.

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