Memory array with power-efficient read architecture

• US 8,811,084 B2
• Filed: 08/30/2012
• Issued: 08/19/2014
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/599,962
• Publication Number:
  US 20140063959A1
• Time in Patent Office: 719 Days
• Field of Search: 365/185.05, 365/185.17, 365/185.18, 365/185.23, 365/51, 365/63
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

Claims

1. An apparatus, comprising:

a first string of memory cells;

a second string of memory cells, the second string of memory cells being configured to receive at least a portion of a current flowing in the first string of memory cells during a read operation; and

a common node coupled between the first string and the second string, the common node comprising a common source.

2. The apparatus of claim 1, wherein the apparatus is configured to electrically couple the second string to the first string through the common node during a read operation.

3. The apparatus of claim 1, further comprising:

a first select transistor coupled to the first string; and

a second select transistor coupled to the second string.

4. The apparatus of claim 3, further comprising:

a third select transistor coupled between the first string and the common node; and

a fourth select transistor coupled between the second string and the common node.

5. The apparatus of claim 3, further comprising:

a first current source;

a first data line coupled to the first select transistor and the first current source, wherein the first select transistor is configured to selectively couple current provided by the first current source to the first string of memory cells;

a second current source; and

a second data line coupled to the second select transistor and the second current source, wherein the second select transistor is configured to selectively couple current provided by the second current source to the second string of memory cells.

6. The apparatus of claim 5, wherein the first current source comprises a first power enable element coupled to the first data line and wherein the second current source comprises a second power enable element coupled to the second data line.

7. The apparatus of claim 6, wherein the first power enable element and the second power enable element are configured to be activated by bias voltages of opposite polarities.

8. The apparatus of claim 5, further comprising a first data enable element and a second data enable element, wherein a first power element is coupled to the first data line through the first data enable element and wherein a second power element is coupled to the second data line through the second data enable element.

9. The apparatus of claim 5, further comprising:

a first sense circuit coupled to the first data line; and

a second sense circuit coupled to the second data line.

10. The apparatus of claim 9, further comprising a first data enable element and a second data enable element, wherein the first sense circuit is coupled to the first data line through the first data enable element and wherein the second sense circuit is coupled to the second data line through the second data enable element.

11. The apparatus of claim 1, wherein the first string of memory cells and the second string of memory cells are each configured to receive separate currents.

12. The apparatus of claim 1, wherein each of the memory cells of the first string are on a respective one of a first number of levels and wherein each of the memory cells of the second string are on a respective one of a second number of levels.

13. The apparatus of claim 12, further comprising:

a third string of memory cells; and

a fourth string of memory cells, a common node being coupled between the third string of memory cells and the fourth string of memory cells, the fourth string of memory cells being configured to receive at least a portion of a current flowing in the third string of memory cells during a read operation.

14. The apparatus of claim 13, wherein the apparatus is configured to couple the first string and the second string to each other in series during a concurrent read operation of the first string and the second string, and wherein the apparatus is configured to couple the third string and the fourth string to each other in series during a concurrent read operation of the third string and the fourth string.

15. The apparatus of claim 13, wherein the first string and the third string are adjacent to one another, and the second string and the fourth string are adjacent to one another.

16. The apparatus of claim 15, wherein each of the memory cells of the third string are on a respective one of the first number of levels and wherein each of the memory cells of the fourth string are on a respective one of the second number of levels.

17. The apparatus of claim 13, further comprising:

a first select transistor coupled to the first string;

a second select transistor coupled to the second string;

a third select transistor coupled to the third string;

a fourth select transistor coupled to the fourth string;

a first current source;

a second current source;

a third current source;

a fourth current source;

a first data line coupled to the first select transistor and the first current source, wherein the first select transistor is configured to selectively couple current provided by the first current source to the first string of memory cells;

a second data line coupled to the second select transistor and the second current source, wherein the second select transistor is configured to selectively couple current provided by the second current source to the second string of memory cells;

a third data line coupled to the third select transistor and the third current source, wherein the third select transistor is configured to selectively couple current provided by the third current source to the third string of memory cells; and

a fourth data line coupled to the fourth select transistor and the fourth current source, wherein the fourth select transistor is configured to selectively couple current provided by the fourth current source to the fourth string of memory cells.

18. The apparatus of claim 12, further comprising:

a third string of memory cells; and

a fourth string of memory cells, wherein each of the memory cells of the third string are on a respective one of a third number of levels and wherein each of the memory cells of the fourth string are on a respective one of a fourth number of levels.

19. The apparatus of claim 1, wherein each of the memory cells within a string are located in different levels of the apparatus.

20. An apparatus, comprising:

a first string of memory cells, each of the memory cells of the first string being on a respective one of a first number of levels; and

a second string of memory cells on a respective one of a second number of levels, the second string of memory cells being configured to receive at least a portion of a current flowing in the first string of memory cells during a read operation.

21. An apparatus comprising:

a number of first strings of memory cells each having a first end and a second end;

a number of second strings of memory cells each having a first end and a second end, the second ends of the second strings being coupled to the second ends of the first strings at a common source; and

a separate data line coupled to each of the number of first strings and the number of second strings, each of the separate data lines being coupled to a separate sense circuit.

22. The apparatus of claim 21, further comprising a separate select transistor coupled to each end of each of the strings of memory cells.

23. An apparatus comprising:

upper strings of memory cells in a first number of levels and including at least a first memory string and a second memory string arranged substantially parallel and adjacent to one another;

lower strings of memory cells in a second number of levels located below the first number of levels and including at least a third memory string and a fourth memory string arranged substantially parallel and adjacent to one another, the upper strings and the lower strings being couplable to each other through a common node; and

a separate sense circuit coupled to each of the memory strings.

24. The apparatus of claim 23, further comprising a separate current source coupled to each of the memory strings.

25. The apparatus of claim 23, wherein the upper strings and the lower strings are configured to be coupled to the common node by select transistors coupled to the memory strings.

26. The apparatus of claim 25, wherein the select transistors are configured to couple the first memory string to the third memory string and to separately couple the second memory string to the fourth memory string.

27. An apparatus comprising:

upper strings including;

a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another; and

a first sense circuit configured to be coupled to the first string of memory cells and a second sense circuit configured to be coupled to the second string of memory cells; and

lower strings including;

a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another; and

a third sense circuit configured to be coupled to the third string of memory cells and a fourth sense circuit configured to be coupled to the fourth string of memory cells, the first string of memory cells and the third string of memory cells being configured to be coupled in series during a read operation and the second string of memory cells and the fourth string of memory cells being configured to be coupled in series during a read operation.

28. The apparatus of claim 27, wherein:

the first string of memory cells and the second string of memory cells are configured to be coupled to a first supply node by power enable elements activated by a bias voltage with a first polarity; and

the third string of memory cells and the fourth string of memory cells are configured to be coupled to a second supply node by power enable elements activated by a bias voltage with a second polarity, the second polarity being opposite the first polarity.

29. The apparatus of claim 27, further comprising select transistors to separately couple the first string of memory cells and the third string of memory cells in series and the second string of memory cells and the fourth string of memory cells in series.

30. The apparatus of claim 29, wherein, during a read operation, the apparatus is configured to perform operations including:

activating the select transistors to couple the first string of memory cells and the third string of memory cells in series;

coupling the first sense circuit and the third sense circuit to the first string of memory cells and the third first string of memory cells, respectively; and

providing a read current through the first string of memory cells and through the third string of memory cells.

31. An apparatus comprising:

a common node;

a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another;

a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another;

a first sense amplifier configured to be coupled to the first string of memory cells and a second sense amplifier configured to be coupled to the second string of memory cells;

a third sense amplifier configured to be coupled to the third string of memory cells and a fourth sense amplifier configured to be coupled to the fourth string of memory cells;

first select transistors to couple the first string of memory cells and the second string of memory cells to the common node;

second select transistors to couple the third string of memory cells and the fourth string of memory cells to the common node; and

a separate current source coupled to each of the memory strings.

32. The apparatus of claim 31, wherein:

the first string of memory cells and the second string of memory cells are configured to be read from concurrently; and

the third string of memory cells and the fourth string of memory cells are configured to be read from concurrently.