Non-volatile memory device and related read method

• US 8,811,087 B2
• Filed: 11/08/2011
• Issued: 08/19/2014
• Est. Priority Date: 02/17/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yun, Eun-jin, Kang, Sang-chul
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/291,389
• Publication Number:
  US 20120213004A1
• Time in Patent Office: 1,015 Days
• Field of Search: 365/185.02, 365/185.09, 365/185.17, 365/185.18, 365/185.21
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells

Abstract

A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.

Claims

1. A nonvolatile memory device, comprising:

a memory cell array comprising a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line;

a voltage generator that provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation; and

a page buffer that senses a level of the bit line after applying a precharge voltage to the bit line in response to a bit line connection signal during the read operation,

wherein the read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor, and wherein a voltage level of the bit line connection signal of a selected memory cell located closest to the string selection transistor is set to be higher than a voltage level of the bit line connection signal for a selected memory cell located closest to the ground selection transistor.

2. The nonvolatile memory device of claim 1, wherein the read voltage of a selected memory cell located closest to the string selection transistor is lower than the read voltage of a selected memory cell located closest to the ground selection transistor.

3. The nonvolatile memory device of claim 1, wherein read voltages of selected memory cells located adjacent to the ground selection transistor are greater by a predetermined amount compared with read voltages of selected memory cells located adjacent to the string selection transistor.

4. The nonvolatile memory device of claim 1, wherein the word lines are divided into at least two groups, and different read voltages are applied to the word lines of each group.

5. The nonvolatile memory device of claim 4, wherein the read voltages applied to the word lines of each group increase from a group located closest to the string selection transistor toward a group located closest to the ground selection transistor.

6. The nonvolatile memory device of claim 1, wherein a voltage level of the bit line connection signal decreases by a predetermined amount from a selected memory cell located closest to the string selection transistor toward a selected memory cell located closest to the ground selection transistor.

7. The nonvolatile memory device of claim 1, wherein the word lines connected to the memory cells are divided into at least two groups, and the bit line connection signal has a different level for each of the at least two groups.

8. The nonvolatile memory device of claim 7, wherein the bit line connection signal for each group decreases from a group located closest to the string selection transistor toward a group located closest to the ground selection transistor.

9. A method of reading a nonvolatile memory device comprising a plurality of strings each comprising a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line, wherein the memory cells of the plurality of strings are organized in pages each connected to a common word line and blocks each comprising a plurality of pages, the method comprising:

identifying a number of program/erase (P/E) cycles of a page in a block corresponding to an address received with a read instruction;

performing a read operation by adjusting a read voltage applied to the page according to a distance between the page and the string selection transistor; and

sensing a level of the bit line after applying a precharge voltage to the bit line in response to a bit line connection signal,

wherein a voltage level of the bit line connection signal for a page located closest to the string selection transistor is set to be higher than a voltage level of the bit line connection signal for a page located closest to the ground selection transistor.

10. The method of claim 9, wherein a read voltage applied to a page located closest to the string selection transistor lower than a read voltage of a page located closest to the ground selection transistor.

11. The method of claim 9, wherein read voltages of memory cells located adjacent to the ground selection transistor are greater by a predetermined amount compared with read voltages of memory cells located adjacent to the string selection transistor.

12. A method of reading a nonvolatile memory device comprising memory cells organized in blocks each comprising a plurality of pages, the method comprising:

receiving a read instruction designating a selected block of memory cells;

identifying a number of program/erase (P/E) cycles for a selected page within the selected block;

adjusting a read voltage or a bit line connection signal for the selected page according to the number of P/E cycles and a distance between the selected page and a string selection transistor or a ground selection transistor; and

performing a read operation on the selected page using the adjusted read voltage or bit line connection signal;

wherein the bit line connection signal is decreased in proportion to the distance between the selected page and the string selection transistor, or increased in proportion to the distance between the selected page and the ground selection transistor.

13. The method of claim 12, wherein the read voltage is decreased in proportion to the distance between the selected page and the ground selection transistor.

14. The method of claim 12, wherein the read voltage is increased in proportion to the distance between the selected page and the string selection transistor.