System for generating difference measurements in a video processor

• US 8,811,485 B1
• Filed: 05/12/2010
• Issued: 08/19/2014
• Est. Priority Date: 05/12/2009
• Status: Expired due to Fees

• Current Assignee: Accumulus Technologies, Inc.
• Original Assignee: Accumulus Technologies, Inc.
• Inventors: Jones, Anthony Mark
• Primary Examiner(s): Ustaris, Joseph
• Assistant Examiner(s): BAILEY, FREDERICK D
• Application Number:
  US12/778,971
• Time in Patent Office: 1,560 Days
• Field of Search: None
• US Class Current: 375/240.16
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/523 with sub-pixel accuracy
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 5/145 Movement estimation for video coding H04N19/51

Abstract

Disclosed are systems and methods used in motion estimation and in other systems where sets of values of numbers are compared. The comparison can use a modified form of summing difference values where portions of the total can be pre-computed. Other difference values can be generated by summing generated filtered values in a cost-effective manner in terms of computing resources and time. The concept of the filtered values can continue to any desired level of refinement. Other concepts disclose multiple methods of computing distance values and systems that can easily switch between the multiple methods.

Claims

1. In a video motion estimation processor, a method of generating a Sum of Absolute Differences (SAD) value for differences between a set of two numbers, the method comprising:

in a processor, creating a first total value equal to a total of all of the numbers in a first set of numbers;

in the processor, creating a second total value equal to a total of all of the numbers in a second set of numbers;

in the processor, combining the first total to the second total to get an intermediate total;

in the processor, determining which of first and second values in the first set of numbers and the second set of numbers, respectively, is the smaller values;

in the processor, doubling the smaller values;

in the processor, summing the doubled smaller values; and

generating a final result SAD value that equals the intermediate total less the doubled smaller value.

2. The method of claim 1, further comprising, for a single video 16×

16 pixel macroblock;

in the processor, generating sixteen SAD values based on a comparison between each pixel of sixteen 4×

4 sub-blocks that make up the macroblock and every possible 4×

4 sub-block at every position in a rectangular candidate array of pixels.

3. The method of claim 2, further comprising, for the single video 16×

16 pixel macroblock;

in the processor, combining the 4×

4 values based on 41 sub-partition tilings defined in the H.264 video standard by simple addition.

4. The method of claim 3, further comprising:

for each of the 41 sub-partition tilings, in the processor, determining a minimum SAD value.

5. A Sum of Absolute Differences (SAD) computation system for a video processor, comprising:

a series of adders structured to accept as input a respective series of numbers and generate a total;

a comparator to determine which of two totals is smaller;

a doubler structured to double the value of a number;

a computation device coupled to the output of the series of adders and structured to accept a first and a second total from the series of adders to generate an intermediate result;

a subtractor coupled to the first computation device and to the doubler, and structured to subtract the double value from the intermediate result.

6. The SAD computation system for a video processor according to claim 5, in which the series of adders is structured to generate a total of a first series of numbers and a total of a second series of numbers.

7. The SAD computation system for a video processor according to claim 6, further comprising a correction circuit.

8. The SAD computation system for a video processor according to claim 7, in which the correction circuit comprises:

a second subtractor having a first and a second input, a subtraction value output and an overflow bit; and

a logic gate structured to combine the overflow bit and the subtraction value output to generate a single correction output.

9. The SAD computation system for a video processor according to claim 8, in which the logic gate is an AND gate having a first input coupled to the subtraction value output and having a second input coupled to a negated value of the overflow bit.