Data writing method, and memory controller and memory storage device using the same

• US 8,812,776 B2
• Filed: 05/22/2012
• Issued: 08/19/2014
• Est. Priority Date: 03/29/2012
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Chang, Ching-Wen
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/477,068
• Publication Number:
  US 20130262747A1
• Time in Patent Office: 819 Days
• Field of Search: 711/103, 711/165, 711/203
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A data writing method for a rewritable non-volatile memory module containing physical blocks is provided. The method includes: configuring virtual block address to map to at least a part of the logical blocks; receiving a write command which instructs to write file data to the first virtual block addresses, and the first virtual block addresses are mapped to first logical blocks of the at least the part of the logical blocks. The method further includes: writing the file data into the physical blocks mapped to a plurality of second logical blocks; determining whether a program failure is occurred during the writing period; and if the program failure is not occurred, the first virtual block addresses are remapped to the second logical block. Accordingly, the method can ensure the update completeness of the file data.

Claims

1. A data writing method, for a rewritable non-volatile memory module comprising a plurality of physical blocks, wherein a plurality of logical blocks are configured to map to a part of the physical blocks, the data writing method comprising:

configuring a plurality of virtual block addresses to map to at least a part of the logical blocks and providing the virtual block addresses to a host system;

receiving a write command from the host system, wherein the write command instructs to write a file data to a plurality of first virtual block addresses of the virtual block addresses, and the first virtual block addresses are mapped to a plurality of first logical blocks among the at least the part of the logical blocks;

writing the file data to the physical blocks mapped to a plurality of second logical blocks of the logical blocks;

determining whether a program failure is occurred when the file data is written to the physical blocks mapped to the second logical blocks; and

if the program failure is not occurred, mapping the first virtual block addresses to the second logical blocks.

2. The data writing method according to claim 1 further comprises:

grouping the logical blocks into at least a storage area and a buffer area, wherein the at least the part of the logical blocks belong the storage area, and the second logical blocks belong to the buffer area,

wherein the step of if the program failure is not occurred, mapping the first virtual block addresses to the second logical block further comprises;

associating the second logical blocks to the storage area, associating the first logical blocks to the buffer area.

3. The data writing method according to claim 2 further comprises:

creating a virtual-logical mapping table for recording a mapping relationship between the virtual block addresses and the logical blocks of the storage area.

4. The data writing method according to claim 3, wherein the step of configuring the virtual block addresses to map to the logical blocks of the storage area and providing the virtual block addresses to the host system comprises:

providing the virtual block addresses to a plurality of application programs executed in the host system,

wherein the step of creating the virtual-logical mapping table comprises;

creating the virtual-logical mapping table for each of the application programs.

5. The data writing method according to claim 1 further comprises:

grouping the physical blocks into at least a data area and a spare area, wherein the logical blocks are mapped to the physical blocks of the data area, the first logical blocks are mapped to a plurality of first physical blocks of the physical blocks of the data area, and the second logical blocks are mapped to a plurality of second physical blocks of the physical blocks of the data area.

6. The data writing method according to claim 5, wherein the step of writing the file data to the physical blocks mapped to the second logical blocks of the logical blocks comprises:

selecting a plurality of third physical blocks from the physical blocks of the spare area;

writing the file data to the third physical blocks;

remapping the second logical blocks to the third physical blocks; and

associating the second physical blocks to the spare area and associating the third physical blocks to the data area.

7. The data writing method according to claim 6 further comprises:

copying valid data belonging to the first logical blocks from the first physical blocks to the third physical blocks.

8. The data writing method according to claim 1 further comprises:

if the program failure is occurred, sending an error message to the host system to respond to the write command.

9. The data writing method according to claim 1, wherein the first logical blocks are mapped to a plurality of first physical blocks of the physical blocks, the second logical blocks are mapped to a plurality of second physical blocks of the physical blocks, and the step of writing the file data into the physical blocks mapped to the second logical blocks of the logical blocks comprises:

writing the file data to the second physical blocks; and

copying valid data belonging to the first logical blocks from the first physical blocks to the second physical blocks.

10. A memory storage device comprising:

a connector, configured to couple to a host system;

a rewritable non-volatile memory module including a plurality of physical blocks, wherein a plurality of logical blocks are configured to map to a part of the physical blocks; and

a memory controller, coupled to the connector and the rewritable non-volatile memory module,

wherein the memory controller configures a plurality of virtual block addresses to map to at least a part of the logical blocks, and provides the virtual block addresses to the host system,

wherein the memory controller receives a write command from the host system, wherein the write command instructs to write a file data to a plurality of first virtual block addresses of the virtual block addresses, and the first virtual block addresses are mapped to a plurality of first logical blocks among the at least the part of the logical blocks,

wherein the memory controller writes the file data to the physical blocks mapped to a plurality of second logical blocks of the logical blocks,

wherein the memory controller determines whether a program failure is occurred when the file data is written to the physical blocks mapped to the second logical blocks,

when the program failure is not occurred, the memory controller maps the first virtual block addresses to the second logical blocks.

11. The memory storage device according to claim 10, wherein the memory controller is configured to group the logical blocks into at least a storage area and a buffer area, wherein the at least the part of the logical blocks belong the storage area, and the second logical blocks belongs to the buffer area,

when the program failure is not occurred, the memory controller associates the second logical blocks to the storage area and associates the first logical blocks to the buffer area.

12. The memory storage device according to claim 11, wherein the memory controller is further configured to create a virtual-logical mapping table to record a mapping relationship between the virtual block addresses and the logical blocks of the storage area.

13. The memory storage device according to claim 12, wherein the memory controller is further configured to provide the virtual block addresses to a plurality of application programs executed in the host system, and create the virtual-logical mapping tables for each of the application programs.

14. The memory storage device according to claim 10, wherein the memory controller is further configured to logically group the physical blocks into at least a data area and a spare area, wherein the logical blocks are mapped to the physical blocks of the data area, the first logical blocks are mapped to a plurality of first physical blocks of the physical blocks of the data area, and the second logical blocks are mapped to a plurality of second physical blocks of the physical blocks of the data area.

15. The memory storage device according to claim 14, wherein when writing the file data to the physical blocks mapped to the second logical blocks of the logical blocks, the memory controller is further configured to select a plurality of third physical blocks from the physical blocks of the spare area, write the file data into the third physical blocks, remap the second logical blocks to the third physical blocks, associate the second physical blocks to the spare area, and associate the third physical area to the data area.

16. The memory storage device according to claim 15, wherein the memory controller is further configured to copy valid data, which belongs to the first logical blocks, from the first physical blocks to the third physical blocks.

17. The memory storage device according to claim 10, wherein the memory controller is further configured to send an error message to the host system to respond to the write command when the program failure is occurred.

18. A memory controller comprising:

a host interface, coupled to a host system;

a memory interface, coupled to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical blocks, wherein a plurality of logical blocks are configured to map to a part of the physical blocks; and

a memory management circuit, coupled to the host interface and memory interface,

wherein the memory management circuit configures a plurality of virtual block addresses to map to at least a part of the logical blocks, and provides the virtual block addresses to the host system,

wherein the memory management circuit receives a write command from the host system, wherein the write command instructs to write a file data to a plurality of first virtual block addresses of the virtual block addresses, and the first virtual block addresses are mapped to a plurality of first logical blocks among the at least the part of the logical blocks,

wherein the memory management circuit writes the file data to the physical blocks mapped to a plurality of second logical blocks of the logical blocks,

wherein the memory management circuit determines whether a program failure is occurred when the file data is written to the physical blocks mapped to the second logical blocks,

when the program failure is not occurred, the memory management circuit maps the first virtual block addresses to the second logical blocks.

19. The memory controller according to claim 18, wherein the memory management circuit is further configured to group the logical blocks into at least a storage area and a buffer area, wherein the at least the part of the logical blocks belong to the storage area, and the second logical blocks belongs to the buffer area,

when the program failure is not occurred, the memory management circuit associates the second logical blocks to the storage area and associates the first logical blocks to the buffer area.

20. The memory controller according to claim 19, wherein the memory management circuit is further configured to create a virtual-logical mapping table to record a mapping relationship between the virtual block addresses and the logical blocks of the storage area.

21. The memory controller according to claim 20, wherein the memory management circuit is further configured to provide the virtual block addresses to a plurality of application programs executed in the host system, and create the virtual-logical mapping table for each of the application programs.

22. The memory controller according to claim 18, wherein the memory management circuit is further configured to logically group the physical blocks to at least a data area and a spare area, where the logical blocks are mapped to the physical blocks of the data area, the first logical blocks is mapped to a plurality of first physical blocks of the physical blocks of the data area, and the second logical blocks are mapped to a plurality of second physical blocks of the physical blocks of the data area.

23. The memory controller according to claim 22, wherein during the memory management circuit writes the file data to the physical blocks mapped to the second logical blocks of the logical blocks, the memory management circuit is further configured to select a plurality of third physical blocks from the physical blocks of the spare area, write the file data into the third physical blocks, remap the second logical blocks to the third physical blocks, associate the second physical blocks to the spare area, and associate the third physical blocks to the data area.

24. The memory controller according to claim 23, wherein the memory management circuit is further configured to copy valid data, which belongs to the first logical blocks, from the first physical blocks to the third physical blocks.

25. The memory controller according to claim 18, wherein the memory management circuit is further configured to send an error message to the host system to respond to the write command when the program failure is occurred.