Method and apparatus for evaluating and optimizing a signaling system

• US 8,812,918 B2
• Filed: 11/07/2011
• Issued: 08/19/2014
• Est. Priority Date: 02/02/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/290,926
• Publication Number:
  US 20120147986A1
• Time in Patent Office: 1,016 Days
• US Class Current: 714/715
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/242 : by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 1/243 : at the transmitter, using a loop-back
• CPC Class Codes: H04L 1/244 : test sequence generators
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 5/1438 : Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. An integrated circuit comprising:

a transmit circuit operable to output a data signal and its complement as a differential signal over a transmission medium in a first mode of operation; and

the transmit circuit further including circuitry operable to generate a repeating pattern signal and its complement for output as the differential signal in a second mode of operation;

wherein,

the transmit circuit is characterized by a parameter operable to affect reception of the differential signal by a receive circuit,

in the second mode of operation, the integrated circuit is operable to vary the parameter within a set of values over multiple iterations of the repeating pattern signal to identify, in dependence on a signal from the receive circuit, a particular value for the parameter that optimizes a desired signaling characteristic, and

in the first mode of operation, the transmit circuit is operable to apply the particular value as the parameter.

2. The integrated circuit of claim 1, wherein the signal from the receive circuit is dependent on sampling of the differential signal by the receive circuit and wherein, in the second mode of operation, the integrated circuit is operable to identify the particular value in dependence on variation the sampling of the differential signal by the receive circuit.

3. The integrated circuit of claim 1, wherein the transmit circuit includes a data storage element that is operable to receive input data and that is output the data signal as a serial signal.

4. The integrated circuit of claim 1, wherein the particular value is necessarily one of the values in the set of values.

5. The integrated circuit of claim 1, wherein the integrated circuit is operable to interpolate an intermediate value between two values in the set of values, and is operable to identify the intermediate value as the particular value.

6. The integrated circuit of claim 1, wherein the parameter is a timing reference.

7. The integrated circuit of claim 1, wherein the parameter is a voltage reference.

8. The integrated circuit of claim 1, wherein the parameter is one of an equalization coefficient, a crosstalk cancellation coefficient, an output drive level, a termination setting, or a transmit clock offset.

9. The integrated circuit of claim 1, wherein the repeating pattern signal repeats a pattern that is a pseudorandom bit sequence (PRBS).

10. The integrated circuit of claim 1, wherein the parameter is an offset to an exclusive one of the repeating pattern signal or its complement.

11. The integrated circuit of claim 1, wherein the transmit circuit comprises a data storage element operable to receive input data, and wherein the circuitry operable to generate the repeating pattern configures the data storage element in the second mode to at least partially generate the repeating pattern signal.

12. The integrated circuit of claim 11, wherein the data storage element is operable to receive parallel data via a parallel load input and is operable to output the parallel data as a serial output for transmission to the receive circuit as the data signal and its complement.

13. The integrated circuit of claim 11, wherein the data storage element comprises a shift register, and wherein the circuitry operable to generate the repeating pattern is operable to configure the shift register as a linear feedback shift register in the second mode, to generate a pattern of the repeating pattern signal to have a greater bit length than a storage capacity of the shift register.

14. The integrated circuit of claim 13, wherein the shift register is a first shift register and the integrated circuit further comprises a second shift register, the first and second shift registers operable to interleave even and odd bits for transmission of the data signal in the first mode of operation.

15. The integrated circuit of claim 11, wherein the data storage element is operable to generate a pattern of the receiving pattern signal in a manner seeded by data in the data storage element following entry into the second mode.

16. The integrated circuit of claim 1, wherein in the second mode, the integrated circuit is operable to sweep the parameter through the set of values over multiple iterations of the repeating pattern signal to identify the particular value for the parameter.

17. The integrated circuit of claim 1, wherein the parameter is a first parameter, and where:

the transmit circuit is characterized by a second parameter operable to affect reception of the differential signal by the receive circuit;

in the second mode of operation, the integrated circuit is operable to vary the second parameter within a set of values over multiple iterations of the repeating pattern signal to identify, in dependence on a signal from the receive circuit, a particular value for the second parameter that optimizes a desired signaling characteristic; and

in the first mode of operation, the transmit circuit is also operable to apply the particular value for the second parameter as the second parameter.

18. The integrated circuit of claim 17, wherein the integrated circuit is sequentially identify the particular value for the first parameter and subsequently, the particular value of the second parameter, over multiple iterations of the repeating pattern signal.

19. An integrated circuit adapted to communicate a differential signal to a receive circuit over a transmission medium, the integrated circuit comprising:

a transmit circuit;

a data storage element operable to store data for sequential output as a data signal; and

circuitry operable to generate a test signal having a pattern that is repeated over multiple iterations;

wherein

during a second mode of operation, the transmit circuit is operable to output to the transmission medium the test signal and its complement as the differential signal while varying a parameter operable to affect reception of the transmit data output signal by the receive circuit amongst multiple values in a set, and

during a first mode of operation, the transmit circuit is operable to output to the transmission medium the data signal and its complement as the differential signal using a particular value of the parameter identified as a function of a signal received from the receive circuit during the second mode of operation.

20. The integrated circuit of claim 19, wherein the signal received from the receive circuit during the second mode of operation is dependent on signal quality of the differential signal as received by the receive circuit, and wherein the integrated circuit is operable to select the particular value of the parameter in dependence on signal quality of the differential signal as received by the receive circuit for each of the multiple values in the set.

21. The integrated circuit of claim 19, wherein the data storage element is operable to receive parallel input data and output the parallel data as a serial signal.

22. The integrated circuit of claim 19, wherein the parameter is a timing reference.

23. The integrated circuit of claim 19, wherein the parameter is a voltage reference.

24. The integrated circuit of claim 19, wherein the parameter is one of an equalization coefficient, a crosstalk cancellation coefficient, an output drive level, a termination setting, or a transmit clock offset.

25. The integrated circuit of claim 19, wherein the pattern is a pseudorandom bit sequence (PRBS).

26. The integrated circuit of claim 19, wherein the transmit circuit comprises circuitry operable to configure the data storage element to at least partially generate the repeating pattern signal in the second mode.

27. The integrated circuit of claim 26, wherein the data storage element comprises a shift register, and wherein the circuitry is operable to configure the shift register as a linear feedback shift register in the second mode, to generate a pattern of the repeating pattern signal to have a greater bit length than a storage capacity of the shift register.

28. The integrated circuit of claim 26, wherein the shift register is a first shift register and the integrated circuit further comprises a second shift register, the first and second shift registers operable to interleave even and odd bits for transmission of the data signal in the first mode of operation.

29. The integrated circuit of claim 19, wherein in the second mode, the integrated circuit is operable to sweep the parameter through the set of values over multiple repetitions of the pattern in the test signal to identify the particular value for the parameter.

30. The integrated circuit of claim 19, wherein the parameter is a first parameter, and where:

the transmit circuit is characterized by a second parameter operable to affect reception of the differential signal by the receive circuit;

during the second mode of operation, the integrated circuit is operable to vary the second parameter within a set of values over multiple repetitions of the pattern of the test signal to identify, in dependence a signal from the receive circuit, a particular value for the second parameter that optimizes a desired signaling characteristic; and

during the first mode of operation, the transmit circuit is also operable to apply the particular value for the second parameter as the second parameter.

31. A method of selecting a parameter for use by a integrated circuit in transmitting data to a receive circuit over a transmission medium, the parameter operable to affect reception of the differential signal by the receive circuit, the method comprising:

in a first mode of operation, using a transmit circuit to transmit input data to the receive circuit as a differential output signal;

in a second mode of operation, using the transmit circuit to transmit a signal having a repeating pattern and its complement to the receive circuit as the differential output signal while varying the parameter amongst multiple values in a set;

based on a signal from the receive circuit, selecting a particular value of the parameter; and

applying the particular value of the parameter in the first mode of operation.

32. The method of claim 31, wherein the signal from the receive circuit represents signal quality of the differential signal as sampled at the receive circuit, and wherein selecting the particular value includes selecting the particular value to optimize the quality of the differential signal as sampled at the receive circuit.