Method and apparatus for evaluating and optimizing a signaling system

• US 8,812,919 B2
• Filed: 06/12/2013
• Issued: 08/19/2014
• Est. Priority Date: 02/02/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/915,896
• Publication Number:
  US 20130272361A1
• Time in Patent Office: 433 Days
• Field of Search: 714/715, 714/745, 714/708, 714/738, 714/712, 714/716, 714/735, 714/739, 370/242, 370/249, 370/252, 375/224, 375/221
• US Class Current: 714/715
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/242 : by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 1/243 : at the transmitter, using a loop-back
• CPC Class Codes: H04L 1/244 : test sequence generators
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 5/1438 : Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. An integrated circuit, comprising:

circuitry to generate a repeating pattern signal during a test mode;

a receiver to serially receive a signal via at least one electrical conductor from a transmitter, the signal comprising a data signal during a normal mode and a repeating test pattern during the test mode;

circuitry to change during the test mode at least one parameter affecting reception of the signal from the transmitter, such that the repeating test pattern from the transmitter is received using alternate values of the at least one parameter; and

circuitry to compare the repeating pattern signal generated by the circuitry to generate with the repeating test pattern serially received by the receiver during the test mode, to generate a comparison output;

where the circuitry to generate the repeating pattern signal during the test mode is independent of any circuitry used to generate the repeating test pattern received from the transmitter.

2. The integrated circuit of claim 1, where the at least one parameter includes at least one of a timing reference used by the receiver to sample the signal and a voltage threshold used to distinguish logic levels of the data signal at the receiver.

3. The integrated circuit of claim 1, where the at least one parameter comprises a timing offset relative to a timing reference, the timing offset used by the receiver to sample the data signal.

4. The integrated circuit of claim 3, where the circuitry to change the at least one parameter during the test mode is to adjust a setting over a range of values to determine a specific value of the timing offset.

5. The integrated circuit of claim 1, further comprising circuitry to set a specific value of the at least one parameter, responsive to the comparison output, for use in receiving the data signal during the normal mode.

6. The integrated circuit of claim 1, where the circuitry to generate comprises a shift register to store elements of the repeating pattern signal during the test mode, and where the repeating pattern signal has a data length greater than a number of shift elements of the shift register.

7. The integrated circuit of claim 6, where the shift register is a linear feedback shift register.

8. The integrated circuit of claim 7, where the linear feedback shift register is to generate the repeating pattern signal during the test mode.

9. The integrated circuit of claim 1, where the circuitry to generate comprises a linear feedback shift register to generate the repeating pattern signal during the test mode.

10. The integrated circuit of claim 9, where generation of the repeating pattern signal by the linear feedback shift register is seeded by data received from the transmitter.

11. The integrated circuit of claim 1, where the electrical conductor is a differential path conductor and the receiver is to serially receive the signal as a differential signal, and where the receiver comprises a differential receiver.

12. A method of evaluating a value of at least one parameter affecting receipt of a signal by a receiver in an integrated circuit, the signal transmitted from a transmitter over an electrical conductor, the method comprising:

generating a repeating pattern signal at the integrated circuit during a test mode;

receiving the signal from the transmitter, where the signal comprises a data signal during a normal mode and a repeating test pattern during the test mode;

during a first iteration of receiving the repeating test pattern from the transmitter during the test mode, using a first value of the at least one parameter;

during a second iteration of receiving the repeating test pattern from the transmitter during the test mode, using a second value of the at least one parameter, the first and second values being alternate values of the at least one parameter, such that in the respective iterations, the repeating test pattern from the transmitter is received using the alternate values of the at least one parameter; and

comparing the repeating pattern signal generated at the integrated circuit with the repeating test pattern received by the receiver during the test mode, to generate a comparison output;

where generating the repeating pattern signal during the test mode is performed using circuitry of the integrated circuit that is independent of any circuitry used to generate the repeating test pattern received from the transmitter.

13. The method of claim 12, where the at least one parameter includes a timing reference used by the receiver to sample the signal.

14. The method of claim 12, where the at least one parameter includes a voltage threshold used by the receiver to distinguish logic levels of the data signal.

15. The method of claim 12, where the at least one parameter comprises a timing offset relative to a timing reference for use in receiving the data signal, and where the method further comprises using the iterations to determine a specific value of the timing offset for use in receiving the data signal.

16. The method of claim 12, further comprising, setting, based on the comparison output, a specific value of the at least one parameter in the receiver for use in receiving the data signal.

17. The method of claim 12, where generating comprises using a shift register to store digital values of the repeating pattern signal during the test mode, and where the repeating pattern signal has a data length greater than a number of shift elements of the shift register.

18. The method of claim 12, where generating includes using a linear feedback shift register to generate the repeating pattern signal during the test mode.

19. The method of claim 12, where receiving comprises receiving the repeating test pattern from the transmitter as a differential signal over the differential conductor.

20. The method of claim 12, where the method further comprises, responsive to the comparison output, causing offset of temporal position of a transmit clock signal in the transmitter, the transmit clock signal used by the transmitter to transmit the signal.

21. The method of claim 12, where the method further comprises, responsive to the comparison output, causing offset of an output drive level in the transmitter, the output drive level used by the transmitter to represent different logic levels in the signal.

22. The method of claim 12, where the electrical conductor is a first electrical conductor, where the at least one parameter is a first at least one parameter, where the receiver is a first receiver, where the integrated circuit comprises a second receiver to receive a second signal from the transmitter over a second electrical conductor, where at least one second parameter affects receipt of the second signal by the second receiver, and where the method further comprises causing, responsive to the comparison output, adjustment of a value for the at least one second parameter affecting of receipt of the second signal by the second receiver.

23. The method of claim 22, where causing comprises causing offset of at least one of a transmit clock signal, the transmit clock signal used by the transmitter to transmit the second signal, or an output drive level, the output drive level used by the transmitter to represent different logic levels in the second signal.

24. An integrated circuit, comprising:

circuitry to generate a repeating pattern signal during a test mode;

a receiver to serially and differentially receive a signal from a transmitter via at least one electrical conductor, the signal comprising a data signal during a normal mode and the repeating test pattern during the test mode;

circuitry to, in a first iteration, use a first value of at least two alternate values of a parameter to receive the repeating test pattern from the transmitter during the test mode, the parameter affecting receipt of the signal by the receiver, and to, in a second iteration, use a second value of the at least two alternate values of the parameter to receive the repeating test pattern from the transmitter during the test mode, such that the repeating test pattern is received using alternate values of the parameter;

circuitry to compare the repeating pattern signal generated by the circuitry to generate with the repeating test pattern received by the receiver during the test mode, to generate a comparison output; and

circuitry to set a specific value of the parameter for use by the receiver in receiving the data signal, responsive to the comparison output;

where the parameter includes at least one of a timing parameter of the receiver, an equalization parameter or a voltage threshold used by the receiver to distinguish logic levels of the data signal, and where the circuitry to generate the repeating pattern signal during the test mode is independent of any circuitry used to generate the repeating test pattern received from the transmitter.