Speeding up defect diagnosis techniques

• US 8,812,922 B2
• Filed: 03/20/2007
• Issued: 08/19/2014
• Est. Priority Date: 03/20/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Zou, Wei, Tang, Huaxing, Cheng, Wu-Tung
• Primary Examiner(s): NGUYEN, STEVE N
• Application Number:
  US11/688,782
• Publication Number:
  US 20070226570A1
• Time in Patent Office: 2,709 Days
• Field of Search: 714/741, 714/737
• US Class Current: 714/737
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G06F 11/2252 using fault dictionaries
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Claims

1. A method of diagnosing defects in an electronic circuit, the method comprising:

determining a set of one or more fault candidates for the electronic circuit for a set of failing test patterns by using a fault dictionary that describes responses of one or more modeled faults to the failing test patterns;

after determining the set of one or more fault candidates, simulating one or more fault candidates of the determined set using both failing and passing test patterns, wherein only a subset of the total passing test patterns is used during the simulating; and

storing the one or more fault candidates and results of the simulating on one or more non-transitory computer-readable storage media.

2. The method of claim 1, further comprising:

ranking the one or more fault candidates based at least in part on results of the simulating; and

storing the results of the ranking on the one or more non-transitory computer-readable storage media.

3. The method of claim 1, wherein the fault dictionary comprises one or more entries identifying one or more fault candidates and identifying one or more clocks that are associated with scan cells that capture failing bits caused by the one or more fault candidates.

4. The method of claim 1, wherein the fault dictionary comprises information associating one or more circuit clock signals with the one or more fault candidates.

5. The method of claim 1, wherein the fault dictionary comprises one or more entries indicating possible signatures produced by one or more of the failing test patterns.

6. The method of claim 1, wherein the one or more fault candidates for the electronic circuit determined using the fault dictionary are a first portion of the set of one or more fault candidates, the method further comprising determining a second portion of the set of one or more fault candidates using path tracing.

7. The method of claim 1, wherein the determining the set of one or more fault candidates for the electronic circuit for the set of failing test patterns by using the fault dictionary comprises searching the fault dictionary for a compressed signature associated with at least one of the one or more modeled faults.

8. The method of claim 1, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

for a selected fault,

simulating one or more test patterns being applied to the electronic circuit in the presence of the selected fault;

determining test responses to the one or more test patterns that indicate the presence of the selected fault using the simulation; and

storing, on the one or more computer-readable storage media, a fault dictionary entry that identifies the selected fault and identifies the test responses that indicate the presence of the selected fault.

9. The method of claim 1, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

determining, for a selected fault, that a first test pattern and a second test pattern detect the selected fault and produce a same respective signature; and

storing on the one or more non-transitory computer-readable storage media one fault dictionary entry for the first and second failing test patterns.

10. The method of claim 9, wherein the approximate size of the fault dictionary corresponds to a size of a signature, a number of faults in the electronic circuit detectable by the one or more failing test patterns, an average number of unique signatures for faults, and a number of clocks in the electronic circuit.

11. The method of claim 9, wherein determining, for a selected fault, that a first test pattern and a second test pattern detect the selected fault and produce a same respective signature comprises compacting test results from the first test pattern and the second test pattern.

12. The method of claim 9, wherein determining, for a selected fault, that a first test pattern and a second test pattern detect the selected fault and produce a same respective signature comprises compacting test results of the one or more failing test patterns in a simulated multiple-input shift register.

13. The method of claim 1, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

simulating one or more faults in a representation of the electronic circuit as one or more test patterns are applied to the representation;

selecting one or more failing test patterns from the simulation results;

identifying one or more unique failing bit combinations for the selected failing patterns;

creating one or more signatures from the one or more unique failing bit combinations; and

storing the one or more signatures on the one or more non-transitory computer-readable storage media.

14. One or more non-transitory computer-readable storage media containing a fault dictionary made according to the fault dictionary generating method of claim 13.

15. The method of claim 1, wherein the determining the set of one or more fault candidates further comprises generating a compressed signature for at least one pattern in the set of failing test patterns.

16. The method of claim 1, wherein the fault dictionary describes only a portion of possible circuit outputs for one or more of the modeled faults for the failing test patterns.

17. One or more non-transitory computer-readable storage media encoded with instructions which, when executed by a computer, implement a method of diagnosing defects in an electronic circuit, the method comprising:

determining a set of one or more fault candidates for the electronic circuit for a set of failing test patterns by using a fault dictionary that describes responses of one or more modeled faults to the failing test patterns;

after determining the set of one or more fault candidates, simulating one or more fault candidates of the determined set using both failing and passing test patterns, wherein only a subset of the total passing test patterns is used during the simulating; and

storing the one or more fault candidates and results of the simulating.

18. The one or more non-transitory computer-readable storage media of claim 17, wherein the fault dictionary comprises a description of one or more failing test patterns having more than a threshold number of failing bits, wherein the threshold number is greater than one.

19. The one or more non-transitory computer-readable storage media of claim 17, wherein the one or more fault candidates of the determined set are simulated using at least one passing pattern, the method further comprising:

selecting one or more passing test patterns for simulation with one or more of the fault candidates of the electronic circuit, wherein the one or more passing test patterns are selected based at least in part on associations of the one or more passing test patterns with one or more clocks associated with the one or more fault candidates; and

storing the selection.

20. The one or more non-transitory computer-readable storage media of claim 19, the method further comprising determining the associations of the one or more passing test patterns with the one or more clocks based at least in part on a netlist description of the electronic circuit.

21. The one or more non-transitory computer-readable storage media of claim 19, wherein the associations indicate which of the one or more clocks clock scan cells that capture failing bits caused by the one or more fault candidates.

22. The one or more non-transitory computer-readable storage media of claim 19, wherein an association of a respective one of the one or more clocks with the one or more fault candidates is indicated by a single bit.

23. The one or more non-transitory computer-readable storage media of claim 17, the method further comprising:

ranking the one or more fault candidates based at least in part on results of the simulation; and

storing the results of the ranking.

24. The one or more non-transitory computer-readable storage media of claim 17, wherein the fault dictionary comprises one or more entries identifying one or more fault candidates and identifying one or more clocks that are associated with scan cells that capture failing bits caused by the one or more fault candidates.

25. The one or more non-transitory computer-readable storage media of claim 17, wherein the fault dictionary comprises information associating one or more circuit clock signals with the one or more fault candidates.

26. The one or more non-transitory computer-readable storage media of claim 17, wherein the fault dictionary comprises one or more entries indicating possible signatures produced by one or more of the failing test patterns.

27. The one or more computer-readable storage media of claim 17, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

for a selected fault,

simulating one or more test patterns being applied to the electronic circuit in the presence of the selected fault;

determining test responses to the one or more test patterns that indicate the presence of the selected fault using the simulation; and

storing a fault dictionary entry that identifies the selected fault and identifies the test responses that indicate the presence of the selected fault.

28. The one or more non-transitory computer-readable storage media of claim 27, wherein the fault dictionary entry is the only entry in the fault dictionary for the selected fault.

29. The one or more non-transitory computer-readable storage media of claim 27, wherein the fault dictionary entry does not indicate which of the one or more test patterns caused the test responses that indicate the presence of the selected fault to be produced.

30. The one or more non-transitory computer-readable storage media of claim 27, wherein the fault dictionary generating method further comprises repeating the acts of simulating, determining, and storing for multiple additional faults.

31. The one or more non-transitory computer-readable storage media of claim 27, wherein the determining the test responses comprises generating x-bit signatures from full test responses of the electronic circuit to the one or more test patterns.

32. The one or more non-transitory computer-readable storage media of claim 31, wherein the storing the fault dictionary entry comprises storing the corresponding x-bit signatures as the test responses that indicate the presence of the selected fault.

33. The one or more non-transitory computer-readable storage media of claim 32, wherein the x-bit signatures are generated by a simulated multiple-input signature register (MISR).

34. The one or more non-transitory computer-readable storage media of claim 32, wherein the fault dictionary generating method further comprises storing information indicative of which clocks clocked scan cells that captured failing bits indicative of the presence of the selected fault during the simulation.

35. The one or more non-transitory computer-readable storage media of claim 17, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

determining, for a selected fault, that a first test pattern and a second test pattern detect the selected fault and produce a same respective signature; and

storing one fault dictionary entry for the first and second failing test patterns.

36. The one or more non-transitory computer-readable storage media of claim 17, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

simulating one or more faults in a representation of the electronic circuit as one or more test patterns are applied to the representation;

selecting one or more failing test patterns from the simulation results;

identifying one or more unique failing bit combinations for the selected failing patterns;

creating one or more signatures from the one or more unique failing bit combinations; and

storing the one or more signatures.

37. The one or more non-transitory computer-readable storage media of claim 36, wherein the selecting one or more failing test patterns from the simulation results comprises selecting failing test patterns whose simulated results produce fewer than a threshold number of failing bits.

38. The one or more non-transitory computer-readable storage media of claim 36, wherein the fault dictionary generating method is part of a preprocessing phase of an electronic circuit testing method.

39. The one or more non-transitory computer-readable storage media of claim 36, wherein the storing the one or more signatures comprises associating a given signature with a group of two or more faults.

40. The one or more non-transitory computer-readable storage media of claim 36, wherein the group of two or more faults is located in a fan-out free region.

41. A computer comprising:

a processor; and

one or more non-transitory computer-readable storage media encoded with instructions configured to cause the processor to;

determine a set of one or more fault candidates for an electronic circuit for a set of failing test patterns by using a fault dictionary that describes responses of one or more modeled faults to the failing test patterns;

simulate one or more fault candidates of the previously determined set using both failing test patterns and a subset of the total passing test patterns; and

store the one or more fault candidates and results of the simulating.

42. The computer of claim 41, the method further comprising:

ranking the one or more fault candidates based at least in part on results of the simulation; and

storing the results of the ranking on the one or more non-transitory computer-readable storage media.

43. The computer of claim 41, wherein the fault dictionary comprises one or more entries identifying one or more fault candidates and identifying one or more clocks that are associated with scan cells that capture failing bits caused by the one or more fault candidates.

44. The computer of claim 41, wherein the fault dictionary comprises information associating one or more circuit clock signals with the one or more fault candidates.

45. The computer of claim 41, wherein the fault dictionary comprises one or more entries indicating possible signatures produced by one or more of the failing test patterns.

46. The computer of claim 41, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

for a selected fault,

simulating one or more test patterns being applied to the electronic circuit in the presence of the selected fault;

determining test responses to the one or more test patterns that indicate the presence of the selected fault using the simulation; and

storing a fault dictionary entry that identifies the selected fault and identifies the test responses that indicate the presence of the selected fault.

47. The computer of claim 41, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

determining, for a selected fault, that a first test pattern and a second test pattern detect the selected fault and produce a same respective signature; and

storing one fault dictionary entry for the first and second failing test patterns.

48. The computer of claim 41, wherein the fault dictionary that describes responses of the one or more modeled faults to the failing test patterns is generated according to a fault dictionary generating method, the fault dictionary generating method comprising:

simulating one or more faults in a representation of the electronic circuit as one or more test patterns are applied to the representation;

selecting one or more failing test patterns from the simulation results;

identifying one or more unique failing bit combinations for the selected failing patterns;

creating one or more signatures from the one or more unique failing bit combinations; and

storing the one or more signatures.