Interleaving apparatuses and memory controllers having the same
First Claim
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1. An interleaving apparatus, comprising:
- a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data;
an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding;
a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data; and
an output unit configured to output the interleaving data, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups and sequentially store at least another of the plurality of data groups.
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Abstract
An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.
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Citations
12 Claims
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1. An interleaving apparatus, comprising:
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a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data; an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding; a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data; and an output unit configured to output the interleaving data, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups and sequentially store at least another of the plurality of data groups. - View Dependent Claims (2, 3, 4, 5)
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6. A memory controller, comprising:
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a write unit configured to receive write commands and write addresses, buffer input data output from a host device in units having a size of a sector to generate sector unit data, interleave the sector unit data, generate interleaving data based on the interleaving, and to write the interleaving data into at least one memory device in response to the write commands and write addresses, the write unit including, a first buffer unit configured to buffer the input data and generate the sector unit data based on the input data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate the interleaving data, the second buffer unit including a plurality of output buffers configured to store the interleaving data, the second buffer unit being configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups and sequentially store at least another of the plurality of data groups; and a read unit configured to receive read commands and read addresses, read read data from the at least one memory device in response to the read commands and read addresses, generate output data based on the read data, and output the output data to the host device. - View Dependent Claims (7, 8, 9, 10)
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11. A system comprising:
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a memory controller including, a write unit configured to receive write commands and write addresses, buffer input data output from a host device in units having a size of a sector to generate sector unit data, interleave the sector unit data, generate interleaving data based on the interleaving, and to write the interleaving data into at least one memory device in response to the write commands and write addresses, the write unit including, a first buffer unit configured to buffer the input data and generate the sector unit data based on the input data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate the interleaving data, the second buffer unit including a plurality of output buffers configured to store the interleaving data, the second buffer unit being configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups and sequentially store at least another of the plurality of data groups, and a read unit configured to receive read commands and read addresses, read read data from the at least one memory device in response to the read commands and read addresses, generate output data based on the read data, and output the output data to the host device; the host device configured to output the input data and receive the output data; and the at least one memory device configured to receive the interleaving data. - View Dependent Claims (12)
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Specification