×

Cache metadata for implementing bounded transactional memory

  • US 8,813,052 B2
  • Filed: 06/08/2007
  • Issued: 08/19/2014
  • Est. Priority Date: 12/07/2005
  • Status: Active Grant
First Claim
Patent Images

1. A method for improving operations of a bounded transactional memory system using cache metadata in a cache of a central processing unit comprising the operations of:

  • providing a bounded transactional memory application with access to cache metadata in a cache of a central processing unit;

    for every transactional read, setting a cache line metadata transaction-read bit;

    for respective transactional writes, setting a cache line metadata transaction-write bit that designates a speculative write;

    testing for evictions or invalidations of lines marked with the cache line metadata transaction-read bit or the cache line metadata transaction-write bit, the testing performed by determining if an eviction summary register is non-zero, the eviction summary register including state corresponding to each cache line, the state corresponding to a respective cache line propagated to the eviction summary register from the cache line metadata when the respective cache line is evicted or invalidated;

    by the testing, finding that one or more of the lines marked with the cache line metadata transaction-read bit or the cache line metadata transaction-write bit were evicted or invalidated; and

    at commit time, based on the finding that one or more of the lines marked with the cache line metadata transaction-read bit or the cache line metadata transaction-write bit were evicted or invalidated, discarding speculatively written lines and calling a cache metadata invalidate instruction to reset all cache line metadata and the eviction summary register to zero, wherein the discarding the speculatively written lines comprises invalidating the speculatively written lines, the speculatively written lines comprising the lines marked with the cache line metadata transaction-write bit.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×