Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores

• US 8,813,212 B2
• Filed: 02/06/2013
• Issued: 08/19/2014
• Est. Priority Date: 01/26/2010
• Status: Active Grant

• Current Assignee: Frampton E. Ellis
• Original Assignee: Frampton E. Ellis
• Inventors: Ellis, Frampton E.
• Primary Examiner(s): SIMITOSKI, MICHAEL J
• Application Number:
  US13/761,126
• Publication Number:
  US 20130174245A1
• Time in Patent Office: 559 Days
• Field of Search: 726/11, 726/22, 726/30, 713/153, 713/154, 713/194
• US Class Current: 726/11
• CPC Class Codes: G06F 21/50 Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H04L 63/0227 Filtering policies mail message filtering H04L51/212

Abstract

A computer or microchip securely controlled-through a private network and including a secure private unit that is protected by an inner hardware-based access barrier or firewall that denies access to the private unit from a network of computers including the Internet, an unprotected public unit including a network connection, a separate private network connection for the private network in the private unit, a general purpose microprocessor, core or processing unit in the public unit, a master controlling device for the computer or microchip in the private unit; and a secure control bus connecting the master controlling device with the microprocessor, core or processing unit and isolated from input from the network and components of the public unit. The master controlling device securely controls an operation executed by the microprocessor, core or processing unit through the private network to the additional private network connection via the secure control bus.

Claims

1. A computer or microchip configured to be securely controlled-through a private network, said computer or microchip comprising:

at least one secure private unit of said computer or microchip that is protected by an inner hardware-based access barrier or firewall that is configured to deny access to said at least one secure private unit from a network of computers including the Internet;

an unprotected public unit of said computer or microchip, said unprotected public unit including at least one network connection configured to connect to the network of computers including the Internet;

at least a separate private network connection configured for connection to at least said private network of computers, at least said separate private network connection being located in at least said secure private unit of said computer or microchip;

at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall;

at least a master controlling device for the computer or microchip located in said secure private unit; and

a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit, said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and

said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit-through said separate private network to said additional and separate private network connection in said secure private unit and via said secure control bus.

2. The computer or microchip of claim 1, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes.

3. The computer or microchip of claim 2, wherein said master controlling device comprises a non-volatile memory.

4. The computer or microchip of claim 3 wherein said secure control bus provides and ensures direct preemptive control by said master controlling device over said unprotected public unit.

5. The computer or microchip of claim 4, wherein said secure control bus is configured such that it cannot be affected, interfered with, altered, read from or written to, or superseded by any part of said unprotected public unit or by input from said network.

6. The computer or microchip of claim 4, wherein said secure control bus is configured to provide a connection to control a firewall located on the periphery of said computer or microchip.

7. The computer or microchip of claim 4, wherein a secure control bus is configured to connect at least said master controlling device with at least two of said microprocessors, cores or processing units located in said unprotected public unit.

8. The computer or microchip of claim 4, wherein a secure control bus is configured to connect at least said master controlling device with at least six of said microprocessors, cores or processing units located in said unprotected public unit.

9. The computer or microchip of claim 3, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus.

10. The computer or microchip of claim 9, wherein said one or more secondary controllers are located in the unprotected public unit.

11. The computer or microchip of claim 10, wherein said one or more secondary controllers are used to control one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit.

12. The computer or microchip of claim 11, wherein said one or more secondary controllers are integrated with one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit.

13. The computer or microchip of claim 11, wherein said secure control bus is wired, wireless or a channel.

14. A computer or microchip configured to be securely controlled, said computer or microchip comprising:

an inner hardware-based access barrier or firewall communicatively connected to a secure private unit of said computer or microchip that is protected by said inner hardware-based access barrier or firewall that is configured to deny access to said at least one secure private unit from a network of computers including the Internet, said inner hardware-based access barrier or firewall being located between said secure private unit and an unprotected public unit of said computer or microchip, and said unprotected public unit being configured to connect to the network of computers including the Internet;

at least one microprocessor, core or processing unit located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is configured for general purposes and is separate from said inner hardware-based access barrier or firewall;

at least a master controlling device for the computer or microchip located in said secure private unit; and

a secure control bus configured to connect at least said master controlling device with at least said at least one microprocessor, core or processing unit located in said unprotected public unit, and said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and

said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit via said secure control bus.

15. The computer or microchip of claim 14, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes.

16. The computer or microchip of claim 15, wherein said master controlling device comprises a non-volatile memory.

17. The computer or microchip of claim 16, wherein said secure control bus provides and ensures direct preemptive control by said master controlling device over said unprotected public unit.

18. The computer or microchip of claim 17, wherein said secure control bus is configured such that it cannot be affected, interfered with, altered, read from or written to, or superseded by any part of said unprotected public unit or by input from said network.

19. The computer or microchip of claim 17, wherein said secure control bus is wired, wireless or a channel.

20. The computer or microchip of claim 17, wherein said secure control bus is configured to provide a connection to control a firewall located on the periphery of said computer or microchip.

21. The computer or microchip of claim 17, wherein a secure control bus configured to connect at least said master controlling device with at least two of said microprocessors, cores or processing units located in said unprotected public unit.

22. The computer or microchip of claim 17, wherein a secure control bus configured to connect at least said master controlling device with at least six of said microprocessors, cores or processing units located in said unprotected public unit.

23. The computer or microchip of claim 17, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus.

24. The computer or microchip of claim 23, wherein said one or more secondary controllers are located in the unprotected public unit.

25. The computer or microchip of claim 24, wherein said one or more secondary controllers are used to control one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit.

26. The computer or microchip of claim 25, wherein said one or more secondary controllers are integrated with one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit.

27. A computer or microchip configured to be securely controlled, said computer or microchip comprising:

at least a first secure private unit of said computer or microchip that is protected by at least a first inner hardware-based access barrier or firewall that is configured to deny access to said at least one secure private unit from a network of computers including the Internet;

an unprotected public unit of said computer or microchip, said unprotected public unit being configured to connect to the network of computers including the Internet;

at least a second secure private unit that is protected by at least a second hardware-based access barrier or firewall, said second secure private unit including at least one computer or microchip component;

at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall;

at least a master controlling device for the computer or microchip located in at least said first secure private unit; and

a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit and said at least one component in said second secure private unit, and said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and

said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit and said at least one component in said second secure private unit, said secure control being provided by said master controlling device in said first secure private unit via said secure control bus.

28. The computer or microchip of claim 27, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes.

29. The computer or microchip of claim 28, wherein said master controlling device comprises a non-volatile memory.

30. The computer or microchip of claim 29, wherein said secure control bus provides and ensures direct preemptive control by said master controlling device over said unprotected public unit.

31. The computer or microchip of claim 30, wherein said secure control bus is configured such that it cannot be affected, interfered with, altered, read from or written to, or superseded by any part of said unprotected public unit or by input from said network.

32. The computer or microchip of claim 31, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus.

33. The computer or microchip of claim 32, wherein said one or more secondary controllers are located in the unprotected public unit.

34. The computer or microchip of claim 33, wherein said one or more secondary controllers are used to control one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit.

35. The computer or microchip of claim 34, wherein said one or more secondary controllers are integrated with one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit.

36. The computer or microchip of claim 30, wherein said secure control bus is wired, wireless or a channel.

37. The computer or microchip of claim 30, wherein said secure control bus is configured to provide a connection to control a firewall located on the periphery of said computer or microchip.

38. The computer or microchip of claim 30, wherein a secure control bus configured to connect at least said master controlling device with at least two of said microprocessors, cores or processing units located in said unprotected public unit.

39. The computer or microchip of claim 30, wherein a secure control bus configured to connect at least said master controlling device with at least six of said microprocessors, cores or processing units located in said unprotected public unit.