Method of fabricating semiconductor die with through-hole via on saw streets and through-hole via in active area of die

• US 8,815,643 B2
• Filed: 02/07/2011
• Issued: 08/26/2014
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Kuan, Heap Hoe, Chua, Linda Pei Ee
• Primary Examiner(s): KUO, WENSING W
• Application Number:
  US13/021,856
• Publication Number:
  US 20110124156A1
• Time in Patent Office: 1,296 Days
• Field of Search: 438/113, 438/114, 438/462, 438/667, 438/672, 257/E21.499, 257/E23.145
• US Class Current: 438/114
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/2101 Structure
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/221 Disposition
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.

Claims

1. A method of making a semiconductor device, comprising:

forming a semiconductor wafer including active areas separated from each other by saw street guides;

forming contact pads on a first surface of the semiconductor wafer within the active areas;

forming a trench in the saw street guides;

filling the trench with organic material;

forming first vias in the organic material;

forming second vias through the contact pads on the active areas of the semiconductor wafer;

forming conductive traces between the contact pads and first vias;

depositing conductive material in the first vias and second vias to form first conductive vias and second conductive vias, respectively; and

singulating the semiconductor wafer along the saw street guides to separate the active areas of the semiconductor wafer into die.

2. The method of claim 1, further including:

forming redistribution layers (RDLs) on a second surface of the semiconductor wafer that is opposite the first surface; and

forming insulating layers between the RDLs.

3. The method of claim 1, further comprising:

stacking the die; and

electrically interconnecting the die using the first and second conductive vias.

4. The method of claim 1, wherein forming first vias in the organic material comprises forming a first via directly between a first contact pad disposed in a first active area and a second contact pad disposed in a second active area adjacent to the first active area.

5. The method of claim 4, wherein singulating the semiconductor wafer along the saw street guides comprises dicing through a first conductive via disposed in the first via to form a third conductive via that is electrically connected to the first contact pad by a first conductive trace and a fourth conductive via that is electrically connected to the second contact pad by a second conductive trace.

6. The method of claim 1, wherein forming first vias in the organic material comprises forming two of the first vias side by side and directly between a first contact pad disposed in a first active area and a second contact pad disposed in a second active area adjacent to the first active area.

7. The method of claim 6, wherein singulating the semiconductor wafer comprises cutting the semiconductor wafer between two of the first conductive vias.

8. A method of making a semiconductor package, comprising:

forming a semiconductor wafer including die, contact pads disposed on first surfaces of the die, first conductive vias disposed outside a perimeter of the die, second conductive vias disposed in the die, and conductive traces electrically connecting the first conductive vias to the contact pads;

forming redistribution layers (RDLs) on second surfaces of the die opposite the first surfaces;

forming repassivation layers between the RDLs on the second surface of the die;

singulating the semiconductor wafer to separate the die;

stacking the die; and

electrically interconnecting the stacked die using the first and second conductive vias.

9. The method of claim 8, wherein singulating the semiconductor wafer comprises cutting through at least one of the first conductive vias to form a third conductive via electrically connected to a first contact pad by a first conductive trace and a third conductive via electrically connected to a second contact pad by a second conductive trace.

10. The method of claim 8, wherein two of the first conductive vias are formed side by side and directly between a first contact pad disposed on a first die and a second contact pad disposed on a second die adjacent to the first die.

11. The method of claim 10, wherein singulating the semiconductor wafer comprises cutting along a saw street guide disposed between the two of the first conductive vias.

12. A method of making a semiconductor package, comprising:

providing a first die including contact pads and first conductive vias formed along a perimeter of the first die, the first conductive vias electrically connected to the contact pads by conductive traces, the first die further including second conductive vias formed through an active area of the first die;

providing a second die disposed adjacent to the first die; and

electrically connecting the first and second die using bond wires and the first conductive vias.

13. The method of claim 12, wherein two of the first conductive vias are formed side by side.

14. The method of claim 13, further comprising:

providing a semiconductor wafer including the first die and second die and including a third conductive via formed along the perimeter of the second die; and

singulating the semiconductor wafer along a saw street guide disposed between the first and third conductive vias.

15. A method of making a semiconductor device, comprising:

providing a semiconductor wafer including a plurality of semiconductor die and contact pads disposed on a first surface of each semiconductor die;

forming a trench completely through the semiconductor wafer;

depositing an organic material in the trench;

forming first vias in the organic material;

forming second vias in the semiconductor die;

depositing a conductive material in the first vias and second vias to form first conductive vias and second conductive vias; and

forming a plurality of conductive traces to electrically connect the contact pads and the first conductive vias.

16. The method of claim 15, further including:

forming redistribution layers (RDLs) on a second surface of the die opposite the first surface; and

forming insulating layers between the RDLs on the second surface of the die.

17. The method of claim 15, further comprising:

stacking the die; and

electrically interconnecting the stacked die using the first and second conductive vias.

18. The method of claim 15, wherein at least one of the first conductive vias is formed directly between a first contact pad disposed on a first die and a second contact pad disposed on a second die that is adjacent to the first die.

19. The method of claim 18, further comprising singulating the semiconductor wafer through the at least one of the first conductive vias to form a third conductive via that is electrically connected to the first contact pad by a first conductive trace and to form a fourth conductive via that is electrically connected to the second contact pad by a second conductive trace.

20. The method of claim 15, wherein two of the first conductive vias are formed side by side and directly between a first contact pad disposed on a first die and a second contact pad disposed on a second die that is adjacent to the first die.

21. The method of claim 20, further comprising singulating the semiconductor wafer along a saw street guide disposed between the two of the first conductive vias.

22. The method of claim 16, further comprising forming conductive bumps that are electrically connected to the RDLs.

23. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die;

forming a trench to completely sever the semiconductor die;

depositing an organic material in the trench between the severed semiconductor die;

forming a first conductive via through the organic material; and

singulating the semiconductor die through the first conductive via to form a second and third conductive via.

24. The method of claim 23, further including:

forming a contact pad over the semiconductor die; and

forming a conductive trace over the semiconductor die to electrically connect the contact pad and second conductive via.

25. The method of claim 23, further including:

stacking the plurality of semiconductor die; and

electrically connecting the stacked semiconductor die through the second and third conductive vias.

26. The method of claim 23, wherein the first conductive via is formed directly between a first contact pad of a first semiconductor die and a second contact pad of a second semiconductor die.

27. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a first via outside a footprint of the first semiconductor die;

forming a second via in the first semiconductor die; and

depositing a conductive material in the first via and second via to form a first conductive via and a second conductive via.

28. The method of claim 27, further including:

forming a contact pad on a first surface of the first semiconductor die;

forming redistribution layers (RDLs) on a second surface of the die opposite the first surface; and

forming insulating layers between the RDLs on the second surface of the die.

29. The method of claim 27, further comprising:

stacking the die; and

electrically interconnecting the stacked die using the first and second conductive via.

30. The method of claim 27, wherein the first conductive via is formed directly between a first contact pad disposed on the first semiconductor die and a second contact pad disposed on a second semiconductor die adjacent to the first die.