Field effect transistor with narrow bandgap source and drain regions and method of fabrication
First Claim
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1. A transistor comprising:
- a gate dielectric layer formed on a substrate;
a gate electrode formed on the gate dielectric layer; and
a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film that extends directly beneath the gate electrode, wherein the semiconductor film comprises InGaAs; and
wherein the semiconductor film is in situ doped to an n-type conductivity with a silicon (Si) dopant.
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Abstract
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
578 Citations
19 Claims
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1. A transistor comprising:
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a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; and a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film that extends directly beneath the gate electrode, wherein the semiconductor film comprises InGaAs; and
wherein the semiconductor film is in situ doped to an n-type conductivity with a silicon (Si) dopant. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A transistor comprising:
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a substrate comprising a body having a top surface opposite a bottom surface and a pair of sidewalls; a gate dielectric layer on the body along the top surface and the pair of sidewalls of the body; a gate electrode on the gate dielectric layer along the top surface and the pair of sidewalls of the body; and a pair of non-planar source/drain regions on the body on opposite sides of the gate electrode, the pair of non-planar source/drain regions comprising an in situ doped InGaAs film that extends beneath the gate electrode, wherein the InGaAs film is doped to an n-type conductivity with a silicon (Si) dopant. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification