Stacked integrated chips and methods of fabrication thereof

• US 8,816,491 B2
• Filed: 08/05/2013
• Issued: 08/26/2014
• Est. Priority Date: 01/13/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Huang, Jao Sheng
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/958,864
• Publication Number:
  US 20130320531A1
• Time in Patent Office: 386 Days
• Field of Search: 257/698, 257/779, 257/E23.011, 438/127, 438/459, 438/667
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Claims

1. A semiconductor device comprising:

a substrate having a first side and a second side, the second side being opposite the first side;

a through substrate via (TSV) extending from the first side to the second side of the substrate, the TSV comprising;

a conductive fill material;

a liner material surrounding the conductive fill material; and

a protrusion from the first side, the protrusion comprising;

a first portion extending a first height from the first side, the first portion being surrounded by the liner material; and

a second portion having a conductive coating on a first surface of the conductive fill material, the first surface being substantially parallel with the first side of the substrate, the conductive coating and the liner material being vertically separated by the second portion of the protrusion; and

an underfill material surrounding the protrusion of the TSV.

2. The semiconductor device of claim 1, wherein the underfill material directly contacts the conductive fill material in the second portion of the protrusion.

3. The semiconductor device of claim 1, wherein the first height is less than a total height of the protrusion.

4. The semiconductor device of claim 1, wherein the second portion is substantially free from liner material.

5. The semiconductor device of claim 1, wherein the substrate comprises a semiconductor wafer comprising active circuitry on the second side of the substrate.

6. The semiconductor device of claim 1, wherein the liner material comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiC, SiCN, a low k dielectric material, a ultra low k dielectric material, and combinations thereof, wherein the conductive fill material comprises a material selected from the group consisting of copper, aluminum, tungsten, silver, gold, doped polysilicon, and combinations thereof.

7. The semiconductor device of claim 1, further comprising a solder ball on the conductive coating and the underfill material.

8. The semiconductor device of claim 1, wherein the underfill material has a first surface substantially coplanar with a first surface of the conductive coating.

9. A semiconductor device comprising:

a through substrate via (TSV) comprising a conductive fill material extending through a substrate and a first portion of the TSV extending beyond a first surface of the substrate;

an insulating liner surrounding the TSV in the substrate, the insulating liner partially surrounding the first portion of the TSV;

a wetting layer on the conductive fill material of the first portion of the TSV; and

an underfill material surrounding the first portion of the TSV, a portion of the insulating liner, and the wetting layer, the underfill material contacting a portion of the conductive fill material.

10. The semiconductor device of claim 9, further comprising a solder ball on the wetting layer and the underfill material, wherein the wetting layer comprises a nickel/gold layer.

11. The semiconductor device of claim 9, wherein the insulating liner comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiC, SiCN, a low k dielectric material, a ultra low k dielectric material, and combinations thereof, wherein the conductive fill material comprises a material selected from the group consisting of copper, aluminum, tungsten, silver, gold, doped polysilicon, and combinations thereof.

12. The semiconductor device of claim 9, wherein the insulating liner extends a first height beyond the first surface of the substrate, wherein the first portion extends a second height beyond the first surface of the substrate, the second height being greater than the first height.

13. The semiconductor device of claim 9, wherein the wetting layer does not contact the insulating liner.

14. A semiconductor device comprising:

a through substrate via (TSV) comprising a conductive fill material extending through a substrate and a first portion of the TSV extending beyond a first surface of the substrate;

an insulating liner surrounding the TSV in the substrate, the insulating liner forming a sidewall spacer on the first portion of the TSV;

a wetting layer on the conductive fill material of the first portion of the TSV; and

an underfill material surrounding the first portion of the TSV, the underfill material contacting the sidewall spacer, the conductive fill material, and the wetting layer.

15. The semiconductor device of claim 14, wherein the underfill material has a surface substantially coplanar with a surface of the wetting layer.

16. The semiconductor device of claim 15 further comprising a solder ball contacting the first surfaces of the wetting layer and the underfill material.

17. The semiconductor device of claim 14, wherein the conductive fill material further comprises a trench liner, the trench liner contacting a second surface of the wetting layer, the second surface being opposite the first surface.

18. The semiconductor device of claim 14, wherein the conductive fill material further comprises a trench liner, the trench liner being coterminous with the sidewall spacer.

19. The semiconductor device of claim 14, wherein the insulating liner comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiC, SiCN, a low k dielectric material, a ultra low k dielectric material, and combinations thereof, wherein the conductive fill material comprises a material selected from the group consisting of copper, aluminum, tungsten, silver, gold, doped polysilicon, and combinations thereof.