Single power supply logic level shifter circuit

• US 8,816,720 B2
• Filed: 04/17/2012
• Issued: 08/26/2014
• Est. Priority Date: 04/17/2012
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Kim, Hoki, Hwang, Changku, Shin, Jinuk
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US13/449,018
• Publication Number:
  US 20130271181A1
• Time in Patent Office: 861 Days
• Field of Search: 326/3, 326/68, 326 80- 81, 326/63, 327/333
• US Class Current: 326/81
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 19/017509 Interface arrangements

Abstract

A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.

Claims

1. An integrated circuit comprising:

a first voltage domain having a first logical high state;

a second voltage domain having a second logical high state, the second logical high state being greater than the first logical high state; and

a single power supply logic level shifter circuit having;

a single power supply source;

an input node;

an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain; and

a charge and break circuit including a three gate delay circuit having an input coupled to the output node and an output coupled to a pull-up transistor, the pull-up transistor output coupled to an intermediate node.

2. The integrated circuit of claim 1, wherein the single power supply logic level shifter circuit is included with the second voltage domain.

3. The integrated circuit of claim 1, wherein the single power supply logic level shifter circuit is included a boundary domain disposed between the first voltage domain and the second voltage domain.

4. The integrated circuit of claim 1, wherein the single power supply logic level shifter circuit is disposed external from both of the first voltage domain and the second voltage domain and wherein the single power supply logic level shifter circuit is disposed adjacent to one of the first voltage domain and the second voltage domain.

5. The integrated circuit of claim 1, wherein the single power supply logic level shifter circuit includes a bleeder circuit.

6. The integrated circuit of claim 5, wherein the bleeder circuit is coupled between the single power source and the intermediate node.

7. The integrated circuit of claim 6, wherein the bleeder circuit couples a leakage current to the intermediate node.

8. The integrated circuit of claim 1, wherein the intermediate node is capable of being disconnected the from the single power supply source.

9. A method of shifting logic levels from a first voltage to a second voltage comprising:

the first voltage domain having a first logical high state, the second voltage domain having a second logical high state, the second logical high state being greater than the first logical high state;

shifting an input signal from low to high on an input node in a single power supply logic level shifter circuit;

discharging an output node of the single power supply logic level shifter circuit to a low state, wherein the single power supply logic level shifter circuit is coupled to a single power supply source, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled to a power grid in the second voltage domain, the single power supply including a charge and break circuit including a three gate delay circuit having an input coupled to the output node and an output coupled to a pull-up transistor, the pull-up transistor output coupled to an intermediate node.

10. The method of claim 9, wherein the single power supply logic level shifter circuit includes a bleeder circuit.

11. The method of claim 10, wherein the bleeder circuit is coupled between the single power source and the intermediate node.

12. The method of claim 11, wherein the bleeder circuit couples a leakage current to the intermediate node.

13. The method of claim 9, wherein the intermediate node is charged to a high state for 3 gate delays and then placed in a floating state.