Body bias circuits and methods

• US 8,816,754 B1
• Filed: 11/02/2012
• Issued: 08/26/2014
• Est. Priority Date: 11/02/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T., Rogenmoser, Robert, Kidd, David A., Kuo, Augustine, McGregor, Michael S.
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US13/668,063
• Time in Patent Office: 662 Days
• Field of Search: 327/534, 327/535, 327/537
• US Class Current: 327/534
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

An integrated circuit can include an operational section comprising a first body bias circuit coupled to drive first body regions to a first bias voltage in response to at least first bias values; a second body bias circuit coupled to drive second body regions to a second bias voltage in response to at least second bias values; a plurality of monitoring sections formed in a same substrate as the operational section, each configured to output a monitor value reflecting a different process variation effect on circuit performance.

Claims

1. An integrated circuit, comprising:

at least one power supply transistor having a source-drain path coupled between a first power supply node and an internal power supply node, and a body coupled to a receive at least a first body bias voltage;

a plurality of monitoring sections formed in a same substrate as the power supply transistor, each configured to output a monitor value reflecting at least one different process variation effect on circuit performance;

a combination logic section configured to generate at least a first bias value by weighting and combining the monitor values;

a first bias circuit configured to generate the first body bias voltage in response to the first bias value; and

a power mode multiplexer circuit configured to selectively apply the first body bias voltage, or a lower body bias voltage to the body of the power supply transistor, the lower body bias voltage having a smaller magnitude and same polarity as the first body bias voltage.

2. The integrated circuit of claim 1, wherein:

at least one of the monitoring sections is a drive monitoring circuit, comprising

at least one transistor under test (TUT) having a source coupled to a first monitor power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node,

at least one monitor capacitor, and

a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first monitor power supply node.

3. The integrated circuit of claim 1, further including:

a core section comprising a plurality of core transistors formed in core body regions coupled to receive the first body bias voltage; and

an offset circuit configured to generate the lower body bias voltage from the first body bias voltage.

4. The integrated circuit of claim 1, further including:

a regulated section comprising a plurality of transistors having sources coupled to the internal power supply node; and

a low dropout regulator circuit, comprising

the power supply transistor, and

an amplifier having a first input coupled to receive a reference voltage, a second input coupled to the regulated section, and an output coupled to a gate of the power supply transistor.

5. The integrated circuit of claim 1, wherein:

the at one power supply transistor comprises a deeply depleted channel transistor having a substantially undoped channel formed over highly doped screening region to provide a strong body coefficient.

6. The integrated circuit of claim 1, further including:

the plurality of monitoring sections include

at least one n-type drive monitoring circuit that includes

at least one n-type transistor under test (TUT) coupled to a first a monitor node,

a first monitor capacitor coupled to the first monitor node, and

at least one p-type drive monitoring circuit that includes

at least one p-type TUT coupled to a second monitor node,

a second monitor capacitor coupled to the second monitor node, and

timing circuits configured to generate monitor values corresponding to rates at which the n-type TUT can transfer current between the first monitor node and a first monitor power supply node, and the p-type TUT can transfer current between the second monitor node and a second monitor power supply node.