Area-optimized analog filter with bandwidth control by a quantized scaling function

• US 8,816,762 B2
• Filed: 01/13/2011
• Issued: 08/26/2014
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Maxlinear Incorporated
• Original Assignee: Maxlinear Incorporated
• Inventors: Fogleman, Eric
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US13/006,334
• Publication Number:
  US 20120025904A1
• Time in Patent Office: 1,321 Days
• Field of Search: 327336-337, 327551-559
• US Class Current: 327/553
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 2210/025 Capacitor
• CPC Class Codes: H03H 2210/036 Stepwise

Abstract

A programmable active frequency-selective circuit includes a first capacitor having a fixed value and a second capacitor coupled in parallel to the first capacitor and having a plurality of switchable capacitors connected in parallel to each other. The programmable active frequency-selective circuit further includes a plurality of switches each being associated with one of the switchable capacitors, and a control port coupled to the switches. The capacitors may be varied to account for processing variations that occur during manufacturing of the programmable active frequency-selective circuit. The capacitors values may also be varied to change the bandwidth and/or gain of the programmable active frequency-selective circuit.

Claims

1. A programmable active frequency-selective circuit comprising:

a first capacitor having a fixed value; and

a second capacitor coupled in parallel with the first capacitor and comprising a plurality of switchable capacitors coupled in parallel to each other;

a lookup table associated with the second capacitor and configured to determine a capacitance value;

a plurality of switches, each of the plurality of switches being associated with a different one of the plurality of switchable capacitors;

a control port configured to control the plurality of switches to achieve the capacitance value using the lookup table; and

a memory coupled to the control port and configured to store the look-up table, wherein the look-up table comprises data associated with gain, bandwidth, and process variations.

2. The programmable active frequency-selective circuit of claim 1 further comprising a memory coupled to the control port and configured to store a software program adapted to program the value of the second capacitor.

3. The programmable active frequency-selective circuit of claim 1 wherein the bandwidth mode is selectable between a first bandwidth and a second bandwidth.

4. The programmable active frequency-selective circuit of claim 1 wherein the gain is programmable between a first gain and a second gain.

5. The programmable active frequency-selective circuit of claim 1 further comprising:

a first resistor having a fixed first value;

a second resistor coupled in series with the first resistor; and

a switch coupled across the second resistor;

wherein the switch is controlled by the control port to short-circuit the second resistor to change a gain of the programmable active frequency-selective circuit.

6. The programmable active frequency-selective circuit of claim 1, wherein the look-up table is accessed by a computer.

7. The programmable active frequency-selective circuit of claim 1, wherein the second capacitor has a common centroid layout and each of the switchable capacitors has a same perimeter-to-area ratio.

8. The programmable active frequency-selective circuit of claim 1, wherein the plurality of switchable capacitors are binary-weighted.

9. A control circuit of a resistor-capacitor (RC) filter, the control circuit comprising:

a first resistor having a first value;

a second resistor connected in series with the first resistor, the second resistor having a second value;

a third resistor having a third value and coupled to the second resistor;

a fixed capacitor coupled across the third resistor;

a capacitor array having a plurality of switchable capacitors arranged in parallel and being coupled across the fixed capacitor and across the third resistor;

a lookup table associated with the capacitor array and configured to determine a capacitance value;

an array of switches, each of the switches being associated with a different one of the switchable capacitors;

a control port coupled to the array of switches; and

a memory coupled to the control port and configured to store the look-up table comprising data associated with bandwidth, gain, and process variations.

10. The control circuit of claim 9, further comprising a memory coupled to the control port and configured to store a software program adapted to program the capacitance value of the capacitor array.

11. The control circuit of claim 9 wherein the memory comprises a RAM, a ROM, or an EEPROM.

12. The control circuit of claim 9, wherein the first, second and third values of the respective first, second, and third resistors are fixed.

13. The control circuit of claim 9 further comprising a switch coupled across the second resistor, wherein the switch is configured to short-circuit the second resistor to change the gain of the RC filter.

14. The control circuit of claim 9, wherein the RC filter is an active low-pass filter having a differential input and a differential output.

15. The control circuit of claim 9, wherein the capacitor array is binary-weighted.

16. The control circuit of claim 9, wherein the RC filter comprises an operational amplifier, the operational amplifier comprising:

an input terminal coupled to the second resistor;

an output terminal coupled to the third resistor;

wherein the fixed capacitor and the capacitor array are coupled across the input terminal and the output terminal.

17. The control circuit of claim 9, wherein the capacitor array has a common centroid layout and each of the switchable capacitors has a same perimeter-to-area ratio.