Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- m×
n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2;
m word lines each connected to n memory cells in a corresponding one of the rows of the m×
n memory cells;
n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×
n memory cells;
a word line drive circuit configured to selectively activate the m word lines;
a write driver configured to supply a rewrite voltage;
a first selection circuit includingn first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, andn second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and
a second selection circuit includingn third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and
n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines.
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Accused Products
Abstract
Each of m word lines is connected to n memory cells in a corresponding one of rows of m×n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m×n memory cells, and each of n source lines is connected to m memory cells in a corresponding one of columns of m×n memory cells. N first switching elements switch connection states between a reference node and the n bit lines, and n second switching elements switch connection states between the reference node and the n source lines. N third switching elements switch connection states between the write driver and the n bit lines, and n fourth switching elements switch connection states between the write driver and the n source lines.
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Citations
17 Claims
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1. A nonvolatile semiconductor memory device comprising:
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m×
n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2;m word lines each connected to n memory cells in a corresponding one of the rows of the m×
n memory cells;n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×
n memory cells;a word line drive circuit configured to selectively activate the m word lines; a write driver configured to supply a rewrite voltage; a first selection circuit including n first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, and n second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and a second selection circuit including n third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A nonvolatile semiconductor memory device comprising:
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a plurality of memory blocks; m word lines, where m is an integer greater than or equal to 2; a word line drive circuit; and first and second select control circuits, wherein each of the memory blocks includes m×
n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2;n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×
n memory cells;a write driver configured to supply a rewrite voltage; a first selection circuit including n first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, and n second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and a second selection circuit including n third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines, each of the m word lines correspond to a different one of the m rows of the m×
n memory cells in the memory blocks, and is connected to n memory cells included in the row corresponding to the word line,the word line drive circuit selectively activates the m word lines, the first select control circuit controls the n first switching elements and the n second switching elements included in the first selection circuit of each of the memory blocks, and the second select control circuit controls the n third switching elements and the n fourth switching elements included in the second selection circuit of each of the memory blocks.
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Specification