Nonvolatile semiconductor memory device

• US 8,817,515 B2
• Filed: 08/01/2013
• Issued: 08/26/2014
• Est. Priority Date: 02/01/2011
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kouno, Kazuyuki
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/957,260
• Publication Number:
  US 20130314969A1
• Time in Patent Office: 390 Days
• Field of Search: 365/65, 365/145, 365/148, 365/158, 365/163, 365/189.14, 365/189.15, 365/189.16, 365/189.17
• US Class Current: 365/65
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/08 for interconnecting magnetic elements, e.g. toroidal cores
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Each of m word lines is connected to n memory cells in a corresponding one of rows of m×n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m×n memory cells, and each of n source lines is connected to m memory cells in a corresponding one of columns of m×n memory cells. N first switching elements switch connection states between a reference node and the n bit lines, and n second switching elements switch connection states between the reference node and the n source lines. N third switching elements switch connection states between the write driver and the n bit lines, and n fourth switching elements switch connection states between the write driver and the n source lines.

Claims

1. A nonvolatile semiconductor memory device comprising:

m×

n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2;

m word lines each connected to n memory cells in a corresponding one of the rows of the m×

n memory cells;

n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×

n memory cells;

a word line drive circuit configured to selectively activate the m word lines;

a write driver configured to supply a rewrite voltage;

a first selection circuit including

n first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, and

n second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and

a second selection circuit including

n third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and

n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines.

2. The nonvolatile semiconductor memory device of claim 1, wherein

in a rewrite operation of changing a data value stored in any one of the m×

n memory cells from a first value to a second value,

one of the n first switching elements which corresponds to the bit line connected to the target memory cell is in an on state,

one of the n second switching elements which corresponds to the source line connected to the target memory cell is in an off state,

one of the n third switching elements which corresponds to the bit line connected to the target memory cell is in the off state, and

one of the n fourth switching elements which corresponds to the source line connected to the target memory cell is in the on state.

3. The nonvolatile semiconductor memory device of claim 2, wherein

(n−

1) of the n first switching elements which do not correspond to the bit line connected to the target memory cell are in the on state,

(n−

1) of the n second switching elements which do not correspond to the source line connected to the target memory cell are in the on state,

(n−

1) of the n third switching elements which do not correspond to the bit line connected to the target memory cell are in the off state, and

(n−

1) of the n fourth switching elements which do not correspond to the source line connected to the target memory cell are in the off state.

4. The nonvolatile semiconductor memory device of claim 2, wherein

after completion of the rewrite operation,

the n first switching elements are in the on state,

the n second switching elements are in the on state,

the n third switching elements are in the off state, and

the n fourth switching elements are in the off state.

5. The nonvolatile semiconductor memory device of claim 1, wherein

in a rewrite operation of changing a data value stored in any one of the m×

n memory cells from a second value to a first value,

one of the n first switching elements which corresponds to the bit line connected to the target memory cell is in an off state,

one of the n second switching elements which corresponds to the source line connected to the target memory cell is in an on state,

one of the n third switching elements which corresponds to the bit line connected to the target memory cell is in the on state, and

one of the n fourth switching elements which corresponds to the source line connected to the target memory cell is in the off state.

6. The nonvolatile semiconductor memory device of claim 5, wherein

(n−

1) of the n first switching elements which do not correspond to the bit line connected to the target memory cell are in the on state,

(n−

1) of the n second switching elements which do not correspond to the source line connected to the target memory cell are in the on state,

(n−

1) of the n third switching elements which do not correspond to the bit line connected to the target memory cell are in the off state, and

(n−

1) of the n fourth switching elements which do not correspond to the source line connected to the target memory cell are in the off state.

7. The nonvolatile semiconductor memory device of claim 5, wherein

after completion of the rewrite operation,

the n first switching elements are in the on state,

the n second switching elements are in the on state,

the n third switching elements are in the off state, and

the n fourth switching elements are in the off state.

8. The nonvolatile semiconductor memory device of claim 1, further comprising:

a sense amplifier, wherein

one end of each of the n third switching elements is connected to the write driver and the sense amplifier, and the other end of each of the n third switching elements is connected to a corresponding one of the n bit lines,

one end of each of the n fourth switching elements is connected to the write driver and the sense amplifier, and the other end of each of the n fourth switching elements is connected to a corresponding one of the n source lines,

the write driver supplies the rewrite voltage in a rewrite operation of rewriting a data value stored in any one of the m×

n memory cells, and

the sense amplifier supplies a read voltage in a read operation of reading a data value stored in any one of the m×

n memory cells.

9. The nonvolatile semiconductor memory device of claim 8, wherein

in the read operation of reading a data value stored in any one of the m×

n memory cells,

one of the n first switching elements which corresponds to the bit line connected to the target memory cell is in an off state,

one of the n second switching elements which corresponds to the source line connected to the target memory cell is in an on state,

one of the n third switching elements which corresponds to the bit line connected to the target memory cell is in the on state, and

one of the n fourth switching elements which corresponds to the source line connected to the target memory cell is in the off state.

10. The nonvolatile semiconductor memory device of claim 9, wherein

(n−

1) of the n first switching elements which do not correspond to the bit line connected to the target memory cell is in the on state,

(n−

1) of the n second switching elements which do not correspond to the source line connected to the target memory cell is in the on state,

(n−

1) of the n third switching elements which do not correspond to the bit line connected to the target memory cell is in the off state, and

(n−

1) of the n fourth switching elements which do not correspond to the source line connected to the target memory cell is in the off state.

11. The nonvolatile semiconductor memory device of claim 9, wherein

after completion of the rewrite operation,

the n first switching elements are in the on state,

the n second switching elements are in the on state,

the n third switching elements are in the off state, and

the n fourth switching elements are in the off state.

12. The nonvolatile semiconductor memory device of claim 1, wherein

each of the m×

n memory cells includes

a selection transistor having a gate connected to the word line corresponding to the memory cell, and

a memory element connected to the selection transistor in series between the bit line and the source line corresponding to the memory cell,

the memory element is configured to change a data value stored in the memory element when a pulse voltage higher than a predetermined threshold voltage is applied to both ends of the memory element, and

a voltage difference between the rewrite voltage and the reference voltage is larger than the threshold voltage.

13. The nonvolatile semiconductor memory device of claim 1, wherein

each of the m×

n memory cells includes

a selection transistor having a gate connected to the word line corresponding to the memory cell, and

a variable resistance element connected to the selection transistor in series between the bit line and the source line corresponding to the memory cell.

14. The nonvolatile semiconductor memory device of claim 1, wherein

each of the m×

n memory cells includes

a selection transistor having a gate connected to the word line corresponding to the memory cell, and

a ferroelectric element connected to the selection transistor in series between the bit line and the source line corresponding to the memory cell.

15. The nonvolatile semiconductor memory device of claim 1, wherein

each of the m×

n memory cells includes

a selection transistor having a gate connected to the word line corresponding to the memory cell, and

a magnetic variable resistance element connected to the selection transistor in series between the bit line and the source line corresponding to the memory cell.

16. The nonvolatile semiconductor memory device of claim 1, wherein

each of the m×

n memory cells includes

a selection transistor having a gate connected to the word line corresponding to the memory cell, and

a phase-change element connected to the selection transistor in series between the bit line and the source line corresponding to the memory cell.

17. A nonvolatile semiconductor memory device comprising:

a plurality of memory blocks;

m word lines, where m is an integer greater than or equal to 2;

a word line drive circuit; and

first and second select control circuits, wherein

each of the memory blocks includes

m×

n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2;

n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×

n memory cells;

a write driver configured to supply a rewrite voltage;

a first selection circuit including

n first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, and

n second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and

a second selection circuit including

n third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and

n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines,

each of the m word lines correspond to a different one of the m rows of the m×

n memory cells in the memory blocks, and is connected to n memory cells included in the row corresponding to the word line,

the word line drive circuit selectively activates the m word lines,

the first select control circuit controls the n first switching elements and the n second switching elements included in the first selection circuit of each of the memory blocks, and

the second select control circuit controls the n third switching elements and the n fourth switching elements included in the second selection circuit of each of the memory blocks.