Memory circuit and semiconductor device

• US 8,817,516 B2
• Filed: 01/29/2013
• Issued: 08/26/2014
• Est. Priority Date: 02/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/752,908
• Publication Number:
  US 20130215661A1
• Time in Patent Office: 574 Days
• Field of Search: 365/72, 365/63, 365/104, 365/102, 365/149, 365/148
• US Class Current: 365/72
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

Included is a first transistor for controlling rewriting and reading of a first data, a second transistor for controlling rewriting and reading of a second data, a first inverter including an input terminal for the first data, a second inverter including an input terminal for the second data, a third transistor between an output terminal of the second inverter and the input terminal of the first inverter, a fourth transistors between the output of the first inverter and the input terminal of the second inverter, a fifth transistor for controlling rewriting and reading of the first data in the first capacitor, and a sixth transistor for controlling rewriting and reading of the second data in a second capacitor. The first data and the second data are held in the first capacitor and the second capacitor even while power supply is cut off.

Claims

1. A memory circuit comprising:

a first transistor;

a second transistor;

a first inverter comprising an input terminal connected to one of a source electrode and a drain electrode of the first transistor, and an output terminal;

a second inverter comprising an input terminal connected to one of a source electrode and a drain electrode of the second transistor, and an output terminal;

a third transistor comprising one of a source electrode and a drain electrode connected to the input terminal of the first inverter and the one of the source electrode and the drain electrode of the first transistor, and the other of the source electrode and the drain electrode connected to the output terminal of the second inverter;

a fourth transistor comprising one of a source electrode and a drain electrode connected to the input terminal of the second inverter and the one of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode connected to the output terminal of the first inverter;

a fifth transistor comprising one of a source electrode and a drain electrode connected to the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the third transistor;

a first capacitor comprising a first electrode connected to the other of the source electrode and the drain electrode of the fifth transistor;

a sixth transistor comprising one of a source electrode and a drain electrode connected to the one of the source electrode and the drain electrode of the second transistor and the one of the source electrode and the drain electrode of the fourth transistor; and

a second capacitor comprising a first electrode connected to the other of the source electrode and the drain electrode of the sixth transistor,

wherein each of the fifth transistor and the sixth transistor has an off-state current per channel width of 1 μ

m is 100 zA or lower.

2. The memory circuit according to claim 1,

wherein the fifth transistor is turned on or off in accordance with a first control signal, and

wherein the sixth transistor is turned on or off in accordance with a second control signal.

3. The memory circuit according to claim 1,

wherein each of the first transistor, the second transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor layer whose bandgap is larger than bandgap of silicon.

4. The memory circuit according to claim 1,

wherein each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes crystal parts,

wherein a c-axis in each of the crystal parts is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor layer is formed or a normal vector of a surface of the oxide semiconductor layer,

wherein metal atoms in each of the crystal parts are arranged in a triangular or hexagonal configuration when seen from the direction perpendicular to an a-b plane, and

wherein metal atoms and oxygen atoms in each of the crystal parts are arranged in a layered manner when seen from the direction perpendicular to the c-axis.

5. A semiconductor device comprising:

a cache memory including the memory circuit according to claim 1;

a CPU having a function of reading data stored in the cache memory and performing arithmetic operation of the data;

a first power supply control switch for controlling supply of a power voltage to the CPU;

a second power supply control switch for controlling supply of a power voltage to the cache memory; and

a controller having at least a function of controlling the first and the second power supply control switches independently in accordance with the input signal and an instruction signal inputted from the CPU.