Semiconductor memory device

• US 8,817,525 B2
• Filed: 08/05/2013
• Issued: 08/26/2014
• Est. Priority Date: 08/03/2012
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), Elpida Memory Incorporated (Micron Technology, Inc.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Ishihara, Kazuya, Tamai, Yukio, Nakano, Takashi, Seko, Akiyoshi
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/959,267
• Publication Number:
  US 20140036573A1
• Time in Patent Office: 386 Days
• Field of Search: 365/148
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the resistance of the variable resistance element to a low resistance) is performed by applying a set voltage pulse for a longer time than that for a reset operation (an operation of converting the resistance of the variable resistance element to a high resistance) while limiting, using the selection transistor, an electric current flowing in the set operation to a certain low electric current, and by simultaneously applying the set voltage pulse to the plurality of memory cells.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells arranged in at least one of a row direction and a column direction, each of the plurality of memory cells having a variable resistance element including a first electrode and a second electrode and a selection transistor, one of the first electrode and the second electrode of the variable resistance element being connected to one of input and output terminals of the selection transistor,

the variable resistance element further including a variable resistor between the first electrode and the second electrode, the variable resistor including metal oxide, such that an electrical resistance between the first electrode and the second electrode changes in accordance with application of an electrical stress between the first electrode and the second electrode, thereby storing information in the semiconductor memory device; and

a control circuit configured to control a reset operation and a set operation,

the reset operation being an operation of applying a reset voltage pulse having a first polarity to ends of a memory cell among the memory cells to convert an electrical resistance between the first electrode and the second electrode of the variable resistance element of the memory cell to a high resistance in a high-resistance range,

the set operation being an operation of applying a set voltage pulse having a second polarity opposite to the first polarity to ends of a memory cell among the memory cells to convert an electrical resistance between the first electrode and the second electrode of the variable resistance element of the memory cell to a low resistance in a low-resistance range, wherein

the control circuit is configured to, in the set operation, apply a certain voltage to a control terminal of the selection transistor of the memory cell to limit an upper limit of a set current flowing between the first electrode and the second electrode to a low electric current, and perform control, while limiting the upper limit of the set current to the low electric current, to apply the set voltage pulse to the plurality of memory cells for a longer time than a time during which the reset voltage pulse is applied in the reset operation.

2. The semiconductor memory device according to claim 1, wherein

the time during which the reset voltage pulse is applied is set shorter than a minimum time during which the set voltage pulse is applied, which is required for an electrical resistance between the first electrode and the second electrode after application of the set voltage pulse to be in the low-resistance range to perform the set operation while limiting the upper limit of the set current to the low electric current.

3. The semiconductor memory device according to claim 1, wherein

in a case where the set voltage pulse is applied to ends of the memory cell in the set operation while the set current is limited, the variable resistance element has a characteristic in which an electrical resistance between the first electrode and the second electrode after the set operation changes to a high-resistance side as the upper limit of the set current decreases and in which an electrical resistance between the first electrode and the second electrode after the set operation changes to the high-resistance side as the time during which the set voltage pulse is applied is reduced.

4. The semiconductor memory device according to claim 1, wherein

in the reset operation, the reset voltage pulse is applied without limiting, using the selection transistor, a reset current flowing between the first electrode and the second electrode of the variable resistance element of the memory cell.

5. The semiconductor memory device according to claim 1, wherein

the memory cell array is configured such that the memory cells are arranged in at least column direction,

the control terminals of the selection transistors of memory cells arranged in same column are mutually connected to a word line extending in the column direction, and

the set operation is a simultaneous set operation that is an operation of simultaneously applying the set voltage pulse to a first group of memory cells including a plurality of adjacent memory cells in the column direction in which the control terminals of the selection transistors are connected to the same word line.

6. The semiconductor memory device according to claim 5, wherein

the control circuit controls a sequential reset operation after the simultaneous set operation, the sequential reset operation being an operation of selecting a second group of memory cells including one or more memory cells to be reset from among the first group of memory cells, and sequentially executing the reset operation on the one or more memory cells in the second group of memory cells.

7. The semiconductor memory device according to claim 6, wherein

the memory cell array is divided into a plurality of banks each including the plurality of memory cells, and

the simultaneous set operation for the plurality of memory cells in one of the plurality of banks and the sequential reset operation for a memory cell in another of the plurality of banks are executed in parallel in an identical operation cycle.

8. The semiconductor memory device according to claim 6, wherein

the control circuit controls a verifying operation after the simultaneous set operation and before the sequential reset operation, the verifying operation being an operation of reading resistance states of the variable resistance elements of all memory cells to which the set voltage pulse is applied, again selecting a memory cell for which an electrical resistance between the first electrode and the second electrode of the variable resistance element is not in the low-resistance range, and performing the set operation on the selected memory cell.

9. The semiconductor memory device according to claim 1, wherein

the control circuit controls a forming operation before executing the set operation and the reset operation, the forming operation being an operation of applying an electrical stress between the first electrode and the second electrode of a variable resistance element that is in an initially high-resistance state to convert the electrical resistance between the first electrode and the second electrode to a low resistance.

10. The semiconductor memory device according to claim 1, wherein

each of the selection transistors has an on-resistance lower than at least an upper limit of the low-resistance range.

11. The semiconductor memory device according to claim 1, wherein

the low-resistance range has an upper limit less than or equal to 100 kΩ

, and the high-resistance range has a lower limit greater than or equal to 1 MΩ

.