Semiconductor device

• US 8,817,527 B2
• Filed: 05/09/2012
• Issued: 08/26/2014
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kobayashi, Hidetomo, Fujita, Masashi, Ohmaru, Takuro
• Primary Examiner(s): Le, Vu
• Application Number:
  US13/467,097
• Publication Number:
  US 20120287703A1
• Time in Patent Office: 839 Days
• Field of Search: 365/154, 365/149
• US Class Current: 365/154
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.

Claims

1. A semiconductor device comprising:

a control circuit; and

a processing unit,

wherein the control circuit comprises;

a first circuit;

a second circuit; and

a first memory element,

wherein the processing unit comprises;

a plurality of second memory elements; and

a plurality of flip-flop circuits,

wherein the first circuit counts the number of times of turning on and off the second circuit,

wherein the second circuit generates a signal input to the plurality of second memory elements and the plurality of flip-flop circuits,

wherein in the case where the counted number is higher than or equal to a threshold value, a first data including a first method for storing the signal in the second memory elements and the flip-flop circuits is stored in the first memory element, and in the case where the counted number is lower than the threshold value, a second data including a second method for storing the signal in the second memory elements and the flip-flop circuits is stored in the first memory element, and

wherein the plurality of second memory elements each include a capacitor of which one electrode is electrically connected to a power supply line and a transistor of which one of a source and a drain is electrically connected to the other electrode of the capacitor.

2. The semiconductor device according to claim 1, wherein the processing unit is a central processing unit.

3. The semiconductor device according to claim 1, wherein an off-state current per micrometer in channel width of the transistor is less than or equal to 10 aA/μ

m.

4. The semiconductor device according to claim 1,

wherein the first method is a constant storage method, and

wherein the second method is an end storage method.

5. The semiconductor device according to claim 1, wherein the transistor comprises an oxide semiconductor.

6. The semiconductor device according to claim 1, wherein the control circuit and the processing unit are formed over a same substrate.

7. A semiconductor device comprising:

a control circuit; and

a processing unit,

wherein the control circuit comprises;

a first circuit;

a second circuit;

a first memory element;

a timer; and

an interface,

wherein the processing unit comprises;

a plurality of second memory elements; and

a plurality of flip-flop circuits,

wherein the first circuit counts the number of times of turning on and off the second circuit,

wherein the second circuit generates a signal input to the plurality of second memory elements and the plurality of flip-flop circuits,

wherein in the case where the counted number is higher than or equal to a threshold value, a first data including a first method for storing the signal in the second memory elements and the flip-flop circuits is stored in the first memory element, and in the case where the counted number is lower than the threshold value, a second data including a second method for storing the signal in the second memory elements and the flip-flop circuits is stored in the first memory element, and

wherein the plurality of second memory elements each include a capacitor of which one electrode is electrically connected to a power supply line and a transistor of which one of a source and a drain is electrically connected to the other electrode of the capacitor.

8. The semiconductor device according to claim 7, wherein the processing unit is a central processing unit.

9. The semiconductor device according to claim 7, wherein an off-state current per micrometer in channel width of the transistor is less than or equal to 10 aA/μ

m.

10. The semiconductor device according to claim 7,

wherein the first method is a constant storage method, and

wherein the second method is an end storage method.

11. The semiconductor device according to claim 7, wherein the transistor comprises an oxide semiconductor.

12. The semiconductor device according to claim 7, wherein the control circuit and the processing unit are formed over a same substrate.

13. A semiconductor device comprising:

a control circuit; and

a processing unit,

wherein the control circuit comprises;

a first circuit;

a second circuit;

a first memory element; and

a logic circuit,

wherein the processing unit comprises;

a plurality of second memory elements; and

a plurality of flip-flop circuits,

wherein the first circuit counts the number of times of turning on and off the second circuit,

wherein the second circuit generates a signal input to the plurality of second memory elements and the plurality of flip-flop circuits,

wherein in the case where the counted number is higher than or equal to a threshold value, a first data including a first method for storing the signal in the second memory elements and the flip-flop circuits is stored in the first memory element, and in the case where the counted number is lower than the threshold value, a second data including a second method for storing the signal in the second memory elements and the flip-flop circuits is stored in the first memory element, and

wherein the plurality of second memory elements each include a capacitor of which one electrode is electrically connected to a power supply line and a transistor of which one of a source and a drain is electrically connected to the other electrode of the capacitor.

14. The semiconductor device according to claim 13, wherein the processing unit is a central processing unit.

15. The semiconductor device according to claim 13, wherein an off-state current per micrometer in channel width of the transistor is less than or equal to 10 aA/μ

m.

16. The semiconductor device according to claim 13,

wherein the first method is a constant storage method, and

wherein the second method is an end storage method.

17. The semiconductor device according to claim 13, wherein the transistor comprises an oxide semiconductor.

18. The semiconductor device according to claim 13, wherein the control circuit and the processing unit are formed over a same substrate.