Current controlled recall schema

• US 8,817,536 B2
• Filed: 12/31/2007
• Issued: 08/26/2014
• Est. Priority Date: 03/22/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Scade, Andreas, Still, David, Allen, James, Ashokkumar, Jay, Johal, Jaskarn Singh
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US12/006,228
• Publication Number:
  US 20080232167A1
• Time in Patent Office: 2,430 Days
• Field of Search: 365/154, 365/156, 365/185.08
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Claims

1. A memory circuit comprising:

a first controlled current source coupled to an input to a nonvolatile cell; and

a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the first controlled current source via the nonvolatile cell;

the first controlled current source providing a substantially constant amount of current to the volatile cell notwithstanding changes in an impedance of the load presented by one or more of the volatile cell and the nonvolatile cell.

2. The memory circuit of claim 1, wherein the second controlled current source coupled to a volatile cell further comprises:

the second current source coupled to reduce potentials between at least two nodes of a latch of the volatile cell.

3. The memory circuit of claim 1, wherein the second controlled current source coupled to a volatile cell further comprises:

at least one pull up transistor and at least one pull down transistor.

4. A RECALL process to cause the state of a nonvolatile memory cell to be represented in a volatile memory cell comprising:

applying a current regulator to prevent premature latching of bit values by a volatile memory cell during a RECALL operation from a nonvolatile memory cell to the volatile memory cell;

the current regulator providing a substantially constant amount of current to the volatile cell notwithstanding changes in an impedance of the load presented by one or more of the volatile cell and the nonvolatile cell.

5. The RECALL process to cause the state of a nonvolatile memory cell to be represented in a volatile memory cell of claim 4, wherein applying a current regulator to prevent premature latching of bit values by a volatile memory cell further comprises:

applying the current regulator to balance a potential between two nodes of a latch of the volatile memory cell.

6. The RECALL process to cause the state of a nonvolatile memory cell to be represented in a volatile memory cell of claim 5, wherein applying the current regulator to balance a potential between two nodes of a latch of the volatile memory cell further comprises:

operating a pull up transistor coupled to a first one of the two nodes, and operating a pull down transistor coupled to a second one of the two nodes.

7. The RECALL process to cause the state of a nonvolatile memory cell to be represented in a volatile memory cell of claim 4, further comprising:

applying a controlled current source to an input of the nonvolatile memory cell during the RECALL.

8. The RECALL process to cause the state of a nonvolatile memory cell to be represented in a volatile memory cell of claim 4, further comprising:

adjusting a voltage at a gate of a nonvolatile charge storage transistor on the nonvolatile memory cell, the voltage at the gate adjusted to reduce a current detected flowing in the current regulator.

9. A memory circuit comprising:

a first controlled current source coupled to an input to a nonvolatile cell; and

a volatile cell coupled to receive current from the first controlled current source via the nonvolatile cell;

the first controlled current source adapted to provide a substantially constant amount of current to the volatile cell via the nonvolatile cell, notwithstanding changes in an impedance of the load presented by one or more of the volatile cell and the nonvolatile cell.

10. The memory circuit of claim 9, further comprising:

a second controlled current source coupled to the volatile cell, the second current source coupled to reduce potentials between at least two nodes of a latch of the volatile cell.

11. The memory circuit of claim 10, wherein the second controlled current source coupled to the volatile cell further comprises:

at least one pull up transistor and at least one pull down transistor.